(19)
(11) EP 0 316 147 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
14.06.1989 Bulletin 1989/24

(43) Date of publication A2:
17.05.1989 Bulletin 1989/20

(21) Application number: 88310525.6

(22) Date of filing: 09.11.1988
(51) International Patent Classification (IPC)4G05F 3/22, G05F 3/28
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 09.11.1987 US 118710

(71) Applicant: TEXAS INSTRUMENTS INCORPORATED
Dallas Texas 75265 (US)

(72) Inventor:
  • Agiman, Dan
    Lewisville Texas 75067 (US)

(74) Representative: Abbott, David John et al
Abel & Imray Northumberland House 303-306 High Holborn
London, WC1V 7LH
London, WC1V 7LH (GB)


(56) References cited: : 
   
       


    (54) High gain driver circuit and method


    (57) Circuitry for providing unlimited, self-adjusted drive current and suitable for power applications is described. A four terminal high efficiency, high gain driver circuit (10) including enabling circuitry is provided along with a positive feedback loop that is designed to provide unlimited drive current which automatically adjusts to the load requirement. The driver circuit includes a startup transistor (14), drive regulation transistors (12,13), predrive transistors (16,18), a driving output transistor (17), and a current splitter (11). The drive regulation transistors (12,13) and the current splitter (11) provide a positive feedback loop which supplies current to the predrive transistors (16,18) and the driving transistor (17). Under typical conditions, feedback loop operation will cause the collector to emitter voltage of the driving transistor (17) to decrease which causes the drive regulation transistors (12,13) to saturate. This condition decreases positive feedback loop drive which in turn regulates the predrive current to the level required by the load. Under short circuit output conditions, the drive regulation transistors (12,13), together with the current splitter (11) and the sensing resistor (29), regulate the output drive current to a predetermined level.







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