(19)
(11) EP 0 316 904 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
20.03.1991 Bulletin 1991/12

(43) Date of publication A2:
24.05.1989 Bulletin 1989/21

(21) Application number: 88119122.5

(22) Date of filing: 17.11.1988
(51) International Patent Classification (IPC)4: G06F 7/48
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 16.11.1987 JP 289912/87

(71) Applicant: NEC CORPORATION
Tokyo (JP)

(72) Inventor:
  • Kojima, Shingo
    Tokyo (JP)

(74) Representative: Glawe, Delfs, Moll & Partner 
Patentanwälte Postfach 26 01 62
80058 München
80058 München (DE)


(56) References cited: : 
   
       


    (54) Arithmetic processor performing mask and trap operations for exceptions


    (57) A floating-point arithmetic processor performing MASK or TRAP operation responsive to occurrence of an exception is disclosed. This processor includes a first flag which is set when the exception occurs, a second flag storing first data designating the MASK operation or second data designating the TRAP operation, a third flag which is set when the first flag is st and the second flag stores the second data, a controller producing a default value in response to the occurrence of the exception, a destination register which is able to be accessed by a CPU, and a transfer gate circuit which takes an open state to allow the default value to be stored into the designation register when the third flag is not set and a closed state to inhibit the default value to be stored into the destination register when the third flag is set.







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