Semiconductor devices with silicon-on-insulator structures

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EP 0 331 811 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	31.01.1990 Bulletin 1990/05

(43)	Date of publication A2:
	13.09.1989 Bulletin 1989/37

(21)	Application number: 88120896.1

(22)	Date of filing: 14.12.1988

(51)	International Patent Classification (IPC)⁴: H01L 21/84, H01L 21/20, H01L 21/268

(84)	Designated Contracting States:
	DE FR GB

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Priority:

18.12.1987 JP 321808/87

(71)	Applicant: FUJITSU LIMITED
	Kawasaki-shi, Kanagawa 211 (JP)

(72)	Inventor:
	Hasegawa, Mitsuhiko c/o FUJITSU LIMITED Kawasaki-shi Kanagawa 211 (JP)

(74)	Representative: Sunderland, James Harry et al
	HASELTINE LAKE & CO Hazlitt House 28 Southampton Buildings Chancery Lane London WC2A 1AT London WC2A 1AT (GB)

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References cited: :

(54)	Semiconductor devices with silicon-on-insulator structures

(57) For fabricating a CMOS SOI structure on a silicon substrate (1) having a (110) plane an insulating SiO₂ layer (2) is formed; an opening (2′) is formed in the SiO₂ layer to expose a part of the substrate (1); a polycrystalline or amorphous silicon layer (3) is deposited on the SiO₂ (2) and in the opening (2′); the deposited silicon layer (3) is divided into islands (3A, 3B) so that a first island (3A) includes the opening (2′) whilst a second island (3B) does not; a laser light (LB) is irradiated onto the islands (3A, 3B) so as to melt the islands; when the laser light irradiation is discontinued the melted islands are recrystallized so that the first island (3AR) forms a (110) plane whilst the second island (3BR) forms a (100) plane; and on the first island (3AR) a p-channel MOS FET is fabricated whilst on the second island (3BR) an n-channel MOS FET is fabricated.

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