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(11) | EP 0 363 567 A3 |
(12) | EUROPEAN PATENT APPLICATION |
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(54) | A computer with interrupt controlled clock speed and its method of operation |
(57) A computer includes a main processing unit having arithmetic logic, memory address
control, input/output address control, and execution control. The computer also has
an operating system program which includes an interrupt handler module. A variable
frequency clock oscillator is disclosed which is controlled by the operating system
via the execution control unit of the main processing unit. Machine level instructions
in the executing program change the clock speed whenever it is necessary to keep the
computer in synchronism with one of its I/O adapters or to speed up the clock when
slow speed circuits are not being utilized. Clock speed is changed by the interrupt
handling module. Circuits and programs, which require longer cycle times to execute
properly, are placed together on interrupt levels. For example, the machine check
program requiring the slowest clock speed is assigned to interrupt level 0. I/O
adapters using low-speed circuitry are assigned to interrupt levels 1, 2 and 3. High
speed circuitry adapters are assigned to interrupt levels 4-7. Whenever an interrupt
is generated, the machine language program serving the interrupt first changes the
speed of the oscillator clock to that speed defined for the interrupt level on which
the interrupt was received. When the interrupt has been serviced, the oscillator clock
speed is restored to that speed of the program operating on the interrupt level which
has just been interrupted. |