(19)
(11) EP 0 363 567 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
10.10.1990 Bulletin 1990/41

(43) Date of publication A2:
18.04.1990 Bulletin 1990/16

(21) Application number: 89111349.0

(22) Date of filing: 22.06.1989
(51) International Patent Classification (IPC)5G06F 1/08
(84) Designated Contracting States:
DE FR GB

(30) Priority: 14.10.1988 US 257664

(71) Applicant: International Business Machines Corporation
Armonk, N.Y. 10504 (US)

(72) Inventors:
  • Antanaitis, Benjamin Charles, Jr.
    Charlotte, NC 28212 (US)
  • Emerson, William Blaine, Jr.
    Matthews, NC 28105 (US)
  • St. John, Joseph Winfield
    Concord, NC 28025 (US)

(74) Representative: Schäfer, Wolfgang, Dipl.-Ing. 
IBM Deutschland Informationssysteme GmbH Patentwesen und Urheberrecht
70548 Stuttgart
70548 Stuttgart (DE)


(56) References cited: : 
   
       


    (54) A computer with interrupt controlled clock speed and its method of operation


    (57) A computer includes a main processing unit having arithmetic logic, memory address control, input/output address control, and execution control. The computer also has an operating system program which includes an interrupt handler module. A variable frequency clock oscillator is disclosed which is controlled by the operating system via the execution control unit of the main processing unit. Machine level instructions in the executing program change the clock speed whenever it is necessary to keep the computer in synchronism with one of its I/O adapters or to speed up the clock when slow speed circuits are not being utilized. Clock speed is changed by the interrupt handling module. Circuits and programs, which require longer cycle times to execute properly, are placed together on interrupt levels. For example, the machine check program re­quiring the slowest clock speed is assigned to inter­rupt level 0. I/O adapters using low-speed circuitry are assigned to interrupt levels 1, 2 and 3. High speed circuitry adapters are assigned to interrupt levels 4-7. Whenever an interrupt is generated, the machine language program serving the interrupt first changes the speed of the oscillator clock to that speed defined for the interrupt level on which the interrupt was received. When the interrupt has been serviced, the oscillator clock speed is restored to that speed of the program operating on the interrupt level which has just been interrupted.







    Search report