Follow-up System for Monitoring the Etching Process in an RIE Equipment and its Application to Producing High-resolution and Reproducible Patterns

Abstract

 A method of producing high-resolution and reproducible patterns, typically polysilicon ultra-fine lines. Accord­ing to a preferred embodiment of the method, a layer of a standard radiation-sensitive resist (17) is applied over a polysilicon layer (16) formed on a substrate (15). The photoresist is delineated as standard in conventional UV lithography equipment to produce a first-resist pattern (17a). The structure is then placed in a Reactive Ion Etching (RIE) equipment and the resist pattern is isotropically eroded to reduce overall dimensions. The etched thickness (dTH) is accurately measured by interferometric techniques, so that the corresponding lateral-dimension reduction (dW) is continuously moni­tored. The etching is terminated when the appropriate lateral-dimension reduction has been obtained to produce a second resist pattern (17a′) of the desired final width (LWf). The second resist pattern (17a′) is then anisotropically transferred to the underlying polysilicon layer (16) by Reactive Ion Etching. Finally, the said second-resist pattern is removed and leaves the desired polysilicon pattern (16a) having the desired final width (LWf). Resist patterns having linewidths in the range of 0,8 µm can be obtained with the maximum resolution of UV lithography equipment known to date. The above method allows resist patterns of smaller linewidths to be pro­duced, which in turn, permits cration of polysilicon lines having widths in the range of 0,6 µm or even less. Such reduced widths are key to the manufacture of gate elec­trode for short-channel CMOS FETs that are necessary for future generations of advanced semiconductor products.

Description

[0001] The present invention relates to the manufacture of ad­vanced semiconductor products, and more particularly to a method for producing sub-micronic patterns through the use of standard photoresist compositions combined with various conventional UV photolithography equipment.

[0002] With the continuous trend towards miniaturized semiconduc­tor devices, e.g. short channel polysilicon gate (0,6 µm) FETs, a tremendous problem to date is to define and con­trol polysilicon line widths smaller than conventional UV photolithography equipment can achieve on standard photoresist layers. With such classic image exposure techniques, the barrier appears to be about 0,8 µm, so that patterns with smaller dimensions cannot be created by transfer from the imaged photoresist layer.

[0003] Enhanced exposure tools for direct image printing, such as excimer lasers and X-ray machines, are not really commer­cially available today, although of high potential inter­est owing to their short operating wavelengths. As far as X-ray machines are concerned, there still remain unsolved problems, such as the difficult fabrication of X-ray masks or membranes, and the production of X-rays (the major source of X-rays is a synchrotron). On the other hand, the use of excimer lasers appears to be limited to pilot or laboratory lines, their extension to manufacturing lines has not been contemplated so far.

[0004] To get rid of these drawbacks, two major techniques were developed a few years ago, which aim to improve the semi­conductor process per se. They are the so-called "sidewall image transfer" (SIT) and the "multilayer resist" (MLR) techniques. Both techniques capitalize on dry etching technologies to produce fine-line geometries with conven­ tional UV photolithography equipment. Dry etching technol­ogies are rapidly displacing wet etching in the fabrica­tion of VLSICs because of their capabilities to give fine-line definition, highly directional etching (anisotropy) and good selectivity, so that precise device fabrication is thereby possible. Basically, dry etching includes plasma etching, a high-pressure process and reactive ion etching or RIE which conversely, is a low-­pressure process. In normal conditions, the latter is only anisotropic, producing vertical profiles in the etched layer: however, as will be demonstrated later, it may become isotropic, provided that it is operated at high pressure.

[0005] In the manufacture of FETs, the SIT technique, basically consists of a sequence of deposition and etching steps that provide submicron FET devices with tight channel control. With to this technique, the line width is only determined by the thickness of a conformal layer that can be very thin and accurate. More details of this technique can be found in US patents 4430791, 4419809, 4419810 and 4648937, assigned to the same assignee as the present invention. Implementing the SIT technique in the semicon­ductor processing may require as many as 21 major steps and 4 specific masks.

[0006] The MLR technique is essentially based on the use of at least two resist layers with an intermediate layer of an etch-resistant barrier material, such as a PECVD oxide, therebetween. Implementation of the MLR technique in the semiconductor processing requires 8 major steps. The MLR technique is described in particular in US patents 3873361 and 4003044, both assigned to the same assignee as the present invention.

[0007] The known MLR technique, when applied to the definition of polysilicon fine-line geometries, such as required in the fabrication of polysilicon gates, is described thereafter, in conjunction with Figs. 1A to 1F.

[0008] Now turning to Fig. 1A, there is shown a semiconductor structure comprising an insulating substrate 10 having a layer 11 of polysilicon (500 nm thick) formed thereon, and a top multilayer photolithographic mask consisting of: a bottom thick (1200 nm) photoresist film 12, an interme­diate 200 nm thick PECVD oxide layer 13, and a top thin (600 nm) photoresist film 14. In CMOS FET technology, the said insulating substrate could be the thin gate silicon dioxide (SiO₂) layer that is formed above the semiconduc­tor (e.g. silicon) body between the source and drain diffusion regions. The polysilicon layer 11 is formed by conventional deposition techniques and is to be patterned in fine line geometries or patterns to define the gate electrodes of CMOS FETs, with determined and precise line widths, e.g. of 0,6 µm, for obtaining high-performance FETs.

[0009] The process of forming this multilayer photolithographic mask is as follows. First, the polysilicon layer 11 is treated by a photoresist adhesion promoter, such as the HexaMethylDiSilazane (HMDS). The bottom resist film is applied by spin coating and dried. Any standard resist is appropriate for this purpose. Then, the thin layer of PECVD oxide is deposited. Low-temperature deposition equipment, such as an Applied Materials type 5000 is adequate. This step is followed by the top resist film coating and bake. Next, after hardening, the top resist film is exposed to UV radiation through a mask having the desired configuration in a conventional UV photolithography equipment. The exposed top resist is developed in a standard KOH solution to leave the desired remaining portion or pattern that is referenced 14a in Fig. 1B. The width LWe′ of pattern 14a is preferably the minimum allowed by the said equipment, when operating at the limits of its resolution specifications, e.g. LWe′ = 0,8 µm. This pattern is subsequently used as an in-situ mask to RIE etch the underlying PECVD oxide layer 13 to define the PECVD pattern 13a. Preferred operating condi­tions are 75 cc CHF3, 5 cc O2 at a pressure of 50 mT (6,6 Pa) and an RF frequency power of 1350 W. The PECVD pattern 13a is then used as an in-situ mask to define a corre­sponding pattern 12a in the bottom thick photoresist layer 12 with vertical walls. This step is achieved in an RIE tool to produce the desired anisotropy with the following typical operating conditions: 50cc O₂ 3cc CF₄, a pressure of 35 mTorrs (4,7 Pa) and an RF frequency power of 1000 W. The addition of a small percentage of CF₄ allows improve­ment of both the etch rate and cleanliness. The resulting structure is shown in Fig. 1B. In the following step, pattern 12a is eroded anisotropically in an RIE tool using the same operating conditions to ensure the desired isotropic etching, i.e. 3cc CF₄ and 50cc O₂, at a pressure of 35 mTorrs and 1000 W. During the overetching step, the lateral dimensions of the pattern are reduced to produce an etch bias of a determined amount dW′. It is important to notice that this an isotropic etching step is a TIME-­controlled process. During this step, the remaining top resist pattern 14a is eliminated. At the end of the overetching step, the lateral dimension of the pattern has diminished by the quantity dwf′ on both sides, so that the final pattern width is LWf′ as illustrated in Fig. 1C. Next, the remaining portion of the PECVD layer 13a is removed using the same operating conditions as given above. The resulting structure is shown in Fig. 1D, where the resist pattern 12a′ that has been obtained from pat­tern 12a after lateral reduction is represented. Finally, pattern 12a′ is used to anisotropically (unidirectional etch) define the desired pattern 11a in the polysilicon layer 11 as shown in Fig. 1E. This last step is performed in different equipment using chlorinated gases as stan­dard. Once the resist pattern 12a′ has been stripped off, the final resulting structure is shown in Fig. 1F. Pattern 11a that is produced by the above MLR process, has a lateral dimension or width LWf′ e.g. 0,6 µm, less than the original dimension LWe′ of 0,8µm. In Fig. 1F, pattern 11a is the schematic cross section of a fine-line geometry, e.g. the gate electrode of an FET. However, it must be understood by the reader, that pattern 11a is part of a whole image including all the line shaped gate electrodes formed at the same time on the wafer substrate. The above fabrication steps are summarized in TABLE 1 below, which makes apparent the existence of six critical steps : 2, 6, 7, 8 , 9 and 10.

TABLE I

[0010] 

1. Pre-treatment and bottom resist coating

2. PECVD OXIDE DEPOSITION

3. Top resist coating

4. Mask alignment and exposure

5. Development

6. PECVD OXIDE RIE ETCHING

7. ANISOTROPIC RESIST RIE ETCHING

8. ANISOTROPIC RESIST RIE OVER ETCHING (TIME control)

9. PECVD OXIDE REMOVAL

10. ANISOTROPIC POLYSILICON RIE ETCHING

11. Resist stripping

[0011] Although the above-described MLR-based process satisfacto­rily solves the problem stated in the introductory part of the present application, it still has a lot of inconve­niences. It is a relatively complex process, involving many processing steps, six of which are critical. In addition, it necessitates the use of a PECVD oxide layer to allow the control of dimensions of the bottom resist pattern during its etching and thus of a specific deposi­tion tool. As a result, it implies the use of different tools. Seen as a whole, it is an expensive process and the manufacturing yields are highly sensitive to contamina­tion. Finally, it is a TIME-controlled process (see step 8 TABLE I,) to perform the over etch. The optimum time is determined empirically, and depends, as known in the art, on many process parameters such as: temperatures, gas pressures, flow rates, etch rates, and RF power. It is therefore clear, that even carefully exercised, the over-­etch step cannot be carefully controlled, which in turn results in a process that has not the required precision and reproducibility. For instance, the final width LWf′ of 0,6 µm is given with a precision of ±0,25 µm (3 σ), with a relatively low reproducibility.

[0012] It is therefore a primary object of the present invention to provide a method of producing high-resolution and reproducible patterns with standard photoresist composi­tions and conventional UV photolithography equipment, beyond the definition that is normally available with this equipment.

[0013] It is another object of the present invention to provide a method of producing high-resolution and reproducible patterns based on a single-layer resist (SLR) process that includes a very few number of critical steps.

[0014] It is still another object of the present invention to provide a method of producing high-resolution and precise patterns avoiding the deposition of an etch-resistant barrier, e.g. a PECVD oxide layer.

[0015] It is still another object of the present invention to provide a method of producing high-resolution and repro­ducible patterns based on a single-layer resist process wherein the definition of lateral dimensions of the fine-­ line geometries or patterns is not achieved by time-con­trol techniques but by accurate thickness control tech­niques.

[0016] It is still another object of the present invention to provide a method of producing high-resolution and reproductible patterns based on the use of a spectrometer operating in an interferometric mode for accurate thick­ness measuring.

[0017] It is yet still another object of the present invention to provide a method of producing high-resolution and repro­ducible patterns based on a single resist-layer process wherein all the isotropic/anisotropic etching steps are completed in situ in a single RIE equipment.

[0018] These objects and others are achieved according to the present invention by a method of producing high-resolution and reproducible patterns in an RIE-etchable material layer formed on a substrate and an innovative monitoring follow-up system for accurate thickness measuring.

[0019] According to a first preferred embodiment, the method includes the steps of :
- forming a radiation-sensitive resist film on the said layer ;
- delineating the said radiation-sensitive resist film to produce a first desired pattern of a first width (LWe) ;
- isotropically etching the said first pattern to reduce both lateral and vertical dimensions ;
- monitoring the vertical dimension reduction, by accurately measuring the etched thickness (dTH) ;
- correlating the corresponding lateral dimension reduction (dW) ;
- terminating the said etching step when the appropri­ate lateral-dimension reduction has been obtained to produce a second derived pattern having the final desired width (LWf) controllably less than the origi­nal first width (LWe) ; and,
- transferring the said second derived pattern to the underlying RIE etchable layer to produce the final desired pattern.

[0020] In a second embodiment, the method includes the steps of :
- delineating the said RIE-etchable material layer to produce a first desired pattern of a first width (LWe) ;
- isotropically etching the said pattern to reduce both lateral and vertical dimensions ;
- monitoring the said vertical-dimension reduction, by accurately measuring the etched thickness (dTH) ;
- correlating the corresponding lateral-dimension reduction (dW) ; and,
- terminating said etching step when the appropriate lateral-dimension reduction has been obtained to produce a second derived pattern having the final desired width (LWf) controllably less than the origi­nal first width (LWe).

[0021] In addition to the said method, the present invention also discloses an innovative monitoring follow-up system where­ in a spectrometer is used in an interferometric mode for accurate etched-thickness measuring.

Figs. 1A to 1F illustrate the details of the fabrication of a submicrometer polysilicon gate according to a method based on the Multi Layer Resist (MLR) technique.

Figs. 2A to 2D illustrate the details of the fabrication of a submicrometer polysilicon gate according to a first preferred embodiment of the method of the present inven­tion based on a single-layer resist (SLR) technique.

Figs. 3A to 3D illustrate the details of the fabrication of a submicrometer polysilicon gate (or a spacer) accord­ing to a second embodiment of the method of the present invention.

Fig. 4 shows standard RIE equipment provided with a con­ventional interferometer and with the innovative spectrom­eter-based follow-up system of the present invention for carrying out the said method.

Fig. 5 is a representation of typical graphical output signals produced by the conventional interferometer and by the follow-up system of the present invention.

[0022] A preferred embodiment of the method of the present inven­tion will now be described in conjunction with Figs. 2A to 2D. In Fig. 2A, there is shown a schematic partial illus­tration of a semiconductor structure cross-section in an intermediate step of the manufacturing. The structure has an insulating substrate 15 having a thin (500 nm) layer 16 of polysilicon and a single relatively thick (1200 nm) film 17 of a standard photoresist material formed thereon according to conventional techniques and with the same specifications as explained above with respect to Fig. 1A. First, the structure is imaged to UV radiations through an appropriate mask in conventional UV photolithographic equipment, then submitted to a post-exposure bake at 95°C, and developed in KOH as standard. The resulting structure is shown in Fig. 2B, where the remaining portion of the photoresist film is referenced 17a. Typical dimensions of pattern 17a after exposure and development are: thickness THe = 0,8 µ m and line width LWe = 0,8 µm. As apparent from Fig. 2B, pattern walls have a typical vertical slope. The structure is now introduced in a standard RIE tool such as an AME 8100 Series Plasma Etch System available from Applied Materials, Inc of Santa Clara, California, USA, and more specifically Model 8110. The standard oper­ating conditions have been significantly changed so that the structure is etched isotropically to decrease the overall dimensions of the photoresist pattern 17a. Experi­ments have shown that appropriate operating conditions for isotropic etch are: 97 cc O₂, 3 cc CF₄ at a pressure of 100 mTorrs (13,3 Pa) and a power of 1350 W. This unusual use of an RIE tool in a different environment (higher pressure and RF power) is considered as being a signifi­cant feature of the invention.

[0023] During the isotropic etch of the pattern, thickness THe is reduced simultaneously with the lateral dimension LWe. It is a key characteristic of the present invention to accu­rately monitor the lateral-dimension reduction dW by the continuous measuring of the pattern-thickness reduction dTH. The technique of correlating the lateral-dimension reduction dW with the etched thickness dTH will be dis­cussed later in more detail. Once the lateral-dimension reduction has reached the desired final value dWf corre­sponding to a determined value dTHf of the etched thick­ness, the etching step is terminated. The resulting struc­ture is shown in Fig. 2C. The process continues as stan­dard, to anisotropically etch the exposed portions of the polysilicon layer 16 in another RIE tool as explained above, to leave the line-haped polysilicon pattern 16a having the desired final-line width LWf that is illustrat­ed in Fig. 2D. It is to be noted that with modern dry-­etching tools such as a Tegal 1511 manufactured by Tegal Corp, Petaluma, California, USA, all the above-mentioned RIE-etching steps can be achieved in the same equipment.

[0024] Still another embodiment is illustrated in conjunction with Figs. 3A to 3D. This alternative can be used for the fabrication of polysilicon spacers. The initial structure is identical to the structure of Fig. 2A except in that the layer of the RIE-etchable material is shown thicker.

[0025] After mask alignment and exposure according to convention­al photolithographic techniques, the remaining photoresist pattern referenced 17b in Fig. 2B is used as an in-situ mask 15 to delineate the underlying polysilicon layer 16, to leave pattern 16b. After the remaining photoresist has been eliminated, the resulting structure is shown in Fig. 3C. The dimensions of the polysilicon pattern 16b are given by its thickness THe and its width LWe (its length, not represented, is immaterial). The structure is now placed in an RIE tool for isotropic etching using fluorinated gases (SF6, NF3, ...) as known by those skilled in the art. During the isotropic etch, the pat­tern-thickness THe is reduced simultaneously with the lateral-dimension LWe. It is still a key feature of the present invention to accurately monitor the lateral-dimen­sion reduction dW by continuous measurement of the pat­tern-thickness reduction dTH. The final structure having the desired final pattern-width LWf is shown in Fig. 3D.

[0026] TABLES II A and B below, briefly summarize the major steps of the method of the present invention according to both embodiments, and makes apparent that it now includes only two critical steps (4, 5, TABLE IIA; 4, 6 TABLE IIB).

TABLE II A

[0027] 

1. Pre-treatment and resist coating

2. Mask alignment and exposure

3. Development

4. ISOTROPIC RESIST RIE ETCHING (THICKNESS control)

5. ANISOTROPIC POLYSILICON RIE ETCHING

6. Resist stripping

TABLE II B

[0028] 

1. Pre-treatment and resist coating

2. Mask alignment and exposure

3. Development

4. ANISOTROPIC POLYSILICON RIE ETCHING

5. Resist stripping

6. ISOTROPIC POLYSILICON RIE ETCHING (THICKNESS control)

[0029] Therefore, irrespective of its various embodiments, the method of the present invention is based on a single layer resist (SLR) process including an isotropic etching step wherein the desired lateral-dimension reduction must be carefully monitored from an accurate measuring of the etched thickness.

[0030] As it appears from the above description, it is of para­mount importance to accurately monitor the lateral-dimen­sion reduction dW by the continuous measuring of the pattern thickness-reduction dTH. Several techniques to control the etched-thickness dTH in a dry-etching environ­ment by measuring some property of the said environment that changes with the thickness could be theoretically envisaged. Ellipsometry, as described in US-A-4198261 utilizes a light source of narrow bandwidth to reflect a light beam from the sample to a light detector. Rotatable polarizing filters are positioned in both the source and the reflected light paths. Intensity of emission is moni­tored to determine the time where it decreases sharply. Optical emission spectroscopy (OES) uses the intensity of the given line having a characteristic wavelength, gener­ated by the plasma, as the control parameter. More details on OES can be found in US-A-4415402, in an application to RIE etching. It is important to note that the spectrometer aperture faces the glow discharge while the wafer is placed horizontally. No interference fringes can be pro­duced in these conditions. The spectrometer detects only a change in intensity. Spectrometry and ellipsometry are useful and extensively used for end-point etch detection. Unlike spectrometric and ellipsometric techniques, optical interferometry uses the variation in the intensity of light beam reflected from the etched portion. It is an accurate technique, that can be used for continuous moni­toring of the etched thickness. Interferometry is the technique that is delivered with the above-mentioned AME RIE tool. The tool is normally provided with an interferometric system that is schematically shown in Fig. 4, where it bears reference 18, while the etching system is referenced 19. The etching system 19 essentially con­sists of an etch-treatment chamber 20 enclosing a hexode-­shaped susceptor 21 that holds a plurality of wafers 22 to be processed. The treatment chamber is provided with two quartz view ports or windows 23A and 23B. One is used by the interferometric system, the other is for visual obser­vation. The interferometric system is referenced 18 in Fig. 4. A laser, such as Helium-Neon laser 24, produces a monochromatic radiation beam 25A that illuminates the wafers at normal incidence through view port 23A. The reflected beam 25B is applied to an interferometer 27 that essentially consists of a photodiode. A beam-splitter 26A and a mirror 26B are used in that respect to appropriately convey incident and reflected beams. The fundamentals of the measuring technique will now be briefly described thereafter. In a preferred operating mode, the optical window views an area of the wafer comparable in size to a portion of a chip. It is therefore guaranteed that both photoresist film and its underlying layer of polysilicon (see Figs. 2A to 2D) are observed. A phase difference exists between rays which is a function of the thickness of the photoresist film and the respective indices of refraction of the film and the layer. Therefore, interfer­ences will occur, producing either greater or lesser intensity of the total reflected energy depending on the magnitude of the phase difference. Since the thickness of layer is decreasing as the etch process continues, the intensity of the energy reflected therefrom will undergo a periodic variation, which is commonly described as the movement of interference fringes. In the case of normal incidence successive minima are separated by a distance which corresponds to the etched thickness during one period T.

[0031] Curve C in Fig. 5 shows the intensity of the output signal produced by photodiode 27 versus time that is obtained with such a HeNe laser, the wavelength of which is λ = 632,8 nm. Each period T′ = 120 sec corresponds to an etched thickness of dTH = 0,17 µm. As known, to increase precision, half a period (maximum of the curve) can be used, by deriving the said output signal. The system referenced 18 in Fig. 4 is not accurate enough to be satisfactorily implemented with the method of the present invention. Of course, other lasers having shorter wave­lengths could be used as well, but they need more space, so that they are not really convenient in a manufacturing environment. In addition, an HeNe laser needs an accurate positioning on a localized and determined area of the chip, as explained above. The HeNe laser interferometer used for etch end point allows the control of the thick­ness erosion for each period during plasma etch, but this laser has a fixed and high wavelength which is not appro­priate for accurate measuring. As a fact, to have good control of the etched thickness it is necessary to cover at least one complete period.

[0032] No adequate system being available, the applicant's inven­tors have developed an innovative and accurate follow-up monitoring system using a standard spectrometer operating in an interferometric mode.

[0033] According to the present invention, there is disclosed the original use of a spectrometer as an interferometer to control the partial removal of the resist until the de­sired final thickness (THf) and therefore the lateral dimension or width (LWf) is reached. The details of the effective follow-up system of the present invention for monitoring the overetch step of the present method e.g. step 4 in TABLE II A of the first embodiment, is also shown in Fig. 4. In Fig. 4, the follow-up system bears reference 28. Interferometry can be used, because with the present method, the intermediate PECVD oxide layer (13, Fig. 1A) does not exist any longer. The plasma inside the treatment chamber produces a glow discharge i.e. a light source where short wavelengths are available with a large choice. Some lines, under certain circumstances, can produce interferences. The glow discharge produced by the plasma can be observed through the view port. This way, an optical spectrometer can be used as an interferometer. Fiber probe 29 is connected to view-port 23B for transmit­ting the radiations emitted by the different species that are produced in the chamber during the etching process. In reality, the follow-up system 28 of the present invention replaces the standard system 18, and uses view-port 23A, still leaving the other view port for visual observation. The transmitted radiation is received by a motor-driven monochromator 30 which filters out all wavelengths except the one selected to be monitored. The characteristic selected radiation is then received by detector 31. Detec­tor 31 may be either a low-noise diode detector or prefer­ably a low-noise photomultiplier tube combined with an amplifier. Monochromator 30 and detector 31 are integral and form the spectrometer 32 e.g. a model SD20 available from the Sofie Inst, Arpajon France. It is tunable over a wide-range spectrum and in the present case is tuned to span the CO line of 309,8 nm. The analog signal supplied by the spectrometer 32 is applied to an A/D converter 33 and then inputted to a computer 34. The signal produced by spectrometer 32 is representative of the intensity of emission of the monitored species. A chart recorder unit 35 is connected to the computer. Also, the latter controls both the motor 36 and the etch-system 19 respectively through control-lines 37 and 38. Computer 34 receives the digital signal that is processed and outputs the intensity of an emission graph that is reproduced by the chart recorder 35. Experimental results conducted in the course of the first embodiment demonstrate that the species to be monitored during the etching of the photoresist pattern 17a atop the polysilicon layer 16 in Fig. 2C, is carbon monoxide CO. It is very important to have the optical fiber connected perpendicular to the wafer for normal incidence to obtain an interferometric-like laser effect with maxima and minima (at zero crossing) of the output signal. When parallel as taught in the prior art, see for instance US patent 4415402 cited above, only a continuous curve illustrating intensity versus time could be record­ed. Experiments have shown that the etched thickness dTH for one period is given below in TABLE III.

TABLE III

λ = 519,8 nm (CO line)	dTH = 0,15 µm
λ = 313,5 nm ( " )	dTH = 0,10 µm
λ = 309,8 nm ( " )	dTH = 0,08 µm

[0034] The shorter the light beam wavelength, the smaller the thickness per period and thus the thickness increment abd precision that can be monitored. High-precision etch control allows good line-width reduction control. With an adequate line (or wavelength, it is possible to get a linewidth LWf control with very small steps for each period.

[0035] Fig. 5 shows curve C that is representative of the inten­sity vs time using the shortest CO radiation (λ = 309,8 nm) for increased precision.

[0036] The final etched thickness dTHf accurately corresponds to the final desired line-width LWf according to the computa­tion that will now be described. The formula that gives the etch-rate ER is given by relation :
ER = (λ/4nT) wherein
λ is the value of the wavelength of the monochromatic radiation produced by the He-Ne laser source (λ= 632, 8 nm) or of the selected line in the glow discharge (e.g. λ = 309,8 nm from the shortest CO line);
n is the refractive index for the material to be etched, say photoresist ; n depends on the layer thickness and the wavelength ; e.g. n = 1,8 for THf = 1 µm and λ= 309,8 nm ; and,
T = time for one period.

[0037] The etch rate for the photoresist can be determined, using the observed time between successive minima or period T, and can be verified on SEM cross sections. The etch-rate ER when known, allows to continuously calculate the etched thickness dTH :
dTH = ER X t
where t is elapsed time.

[0038] When a relation between the etched thickness for one period has been established it is easy to control the lateral dimension reduction.

[0039] The horizontal-to-vertical etch-ratio ERRhv is:
ERRhv = ERh/ERv, where
ERv is the measured vertical-etch rate,
ERh the measured horizontal-etch rate.

[0040] Generally, ERRhv is close to one (ideal isotropy means ERRhv = 1), but in reality accurate monitoring is neces­sary, and the real value of ERRhv must be determined through preliminary experiments. Basically, ERRhv ranges from 0,5 to 0,75 mainly depending on the pattern factor, say the percentage of the wafer that is covered by the photoresist film. The pattern factor is practically ob­tained from the mask.

[0041] Quantity dTh x ERRvh represents the lateral dimension reduction dW per edge, so the total reduction is twice more. At completion of the process:
LWf = LWe - 2dW = L.We - (2 x dTHf x ERRhv)

[0042] This computation allows continuous tight linewidth control and also to reach the final desired linewidth dimension LWf.

[0043] In summary, the standard RIE tool is provided with an HeNe laser source for interferometric measures. But, because of the relatively high wavelength (λ= 632,8 nm), the measure­ment of the etched thickness (dTH) with system 18 is not accurate enough. Fig. 5 shows curve C that illustrates a period T′ of about 120 sec which corresponds to dTH = 0,17 µm. Applicant's inventors have recognized that radiations that are naturally produced by the glow discharge during the etching process, not only have shorter wave­lengths but, may, in certain conditions, also produce interferometric fringes. As a result, the follow-up moni­toring system of the present invention referenced 28 in Fig. 4 provides much higher precision than the known systems. In Fig. 5, curve C is representative of the interferences obtained with the shortest CO line (λ = 309,8 nm) which allows etched thickness as low as dTH = 0,08 µ m with a corresponding period T of about 60 sec. (T is approximately half of T′). As a result, the method of the present invention allows to produce polysilicon line widths of 600 nm with a precision of ±180 nm at 3σ.

[0044] Advantages of the method of producing high-resolution and reproducible patterns of the present invention that is based on the SLR, rather on than the MLR technique, are listed below:
- simpler, cheaper and shorter process (6 instead of 11 steps), 2 of which are critical instead of 6.
- no PECVD oxide deposition required, avoiding the use of costly PECVD tools and permitting use of interferometry.
- lower sensitivity to foreign material contamination and resist pinhole.
- steps 4 and 5 (Table IIA) can be completed in one single RIE equipment such as a Tegal 1511.
- higher resolution and more precise patterns are obtained owing to the accurate in-situ monitoring process control based on precise interferometric measures instead of using a timer.
- better etching uniformity.
- reproducibility.

[0045] More generally, the method of the present invention can be applied to other materials (e.g. oxides, metals, ...), or other processing steps (e.g. resist etch back for self-­aligned process), others applications, etc.

[0046] In addition, an algorithm can be developed to more accu­rately determine the etch end point of the entire batch of wafers.

Claims

1. A method of producing high resolution and reproduc­ible patterns in a structure comprising a layer (16) of an etchable material formed on a substrate (15) characterized in that it includes the steps of :
- forming a radiation-sensitive film (17) on said layer (16) ;
- delineating said radiation-sensitive film to produce a first-resist pattern (17a) of a first-­width (LWe) ;
- isotropically etching said first-resist pattern to reduce both lateral and vertical dimensions;
- monitoring the vertical-dimension reduction, by accurately measuring the etched thickness (dTH);
- correlating the corresponding lateral-dimension reduction (dW) ;
- terminating said etching step when the appropri­ate lateral-dimension reduction (dWf) has been obtained to produce a second derived resist pattern (17a′) having the final desired width (LWf) controllably less than the original first width (LWe) ;

2. The method of claim 1 further includes the step of:
- unidirectionally transferring the said second derived resist pattern to the underlying etchable material layer (16), to produce the final desired pattern (16a) therein with the said final desired width (LWf).

3. The method of claim 1 or 2 further includes the step of:
- stripping away the said second derived resist pattern

4. The method of claim 1, 2 or 3 wherein the said step of unidirectionally transferring the said second derived resist pattern consists of an anisotropic etching in a RIE tool.

5. The method of any above claim wherein the said step of isotropically etching the said first resist pat­tern is achieved in an RIE tool operating at high pressure to produce isotropic etch conditions.

6. The method of claim 5 wherein the operating condi­tions are: 97 cc O2, 3 cc CF4, 100 mTorrs and 1350 W.

7. The method of any claim 4 to 6 wherein the said steps of unidirectionally transferring and of isotropically etching are completed in the same RIE tool.

8. The method of any above claim wherein the step of delineating the said radiation-sensitive film com­prises the steps of:
- exposing said film to UV radiations through a mask having the desired configuration in conven­tional UV lithography equipment operating at the limit of resolution specifications; and,
- developing said film, to produce said first resist pattern (17a).

9. The method according to any above claim wherein the step of monitoring the vertical-dimension reduction comprises the steps of:
- selecting a short wavelength of a species that is produced by the glow discharge that illumi­nates the structure during the step of isotropically etching;
- observing the glow discharge at normal incidence through a spectrometer tuned on the said select­ed wavelength;
- continuously monitoring the output signal pro­duced by said spectrometer to measure the etched thickness.

10. A method of producing high resolution and reproduc­ible patterns in a structure comprising a layer (16) formed on a substrate (15) characterized in that it includes the steps of :
- delineating the said layer (16) to produce a first pattern (16b) of a first width (LWe) ;
- isotropically etching said first pattern to reduce both lateral and vertical dimensions ;
- monitoring the vertical dimension reduction, by accurately measuring the etched thickness (dTH);
- correlating the corresponding lateral dimension reduction (dW);
- terminating the said etching step when the appropriate lateral dimension reduction has been obtained to produce a second derived pattern of lines (16b′) having the final desired width (LWf) controllably less than the original first width (LWe).

11. The method of claim 10 wherein the said step of delineating comprises the steps of:
- forming a radiation-sensitive film (17) on the layer (16);
- exposing the said film to UV radiations through a mask having the desired configuration in conventional UV lithography equipment operating at the limit of resolution specifications;
- developing the said film, to produce a first resist pattern (17b);
- unidirectionally transferring the first resist pattern to the underlying layer to produce the said first pattern (16b).

12. A follow-up system (28) for monitoring the etching process in a RIE equipment (19) having a treatment chamber (20) for containing a plasma and provided with a quartz view port (23), a susceptor (21) that holds a semiconductor wafer (22) bearing a structure to be etched; said system including:
- an optical fiber means (29) disposed close to the view port and perpendicular to said wafer;
- spectrometer means that filters one line of a determined species that is produced during the etching process by the glow discharge to select a characteristic wavelength λ, and generates a variable output signal representative of the intensity of that line having maxima and minima depending on the etched thickness; and
- means for detecting said output signal so that the etched thickness is accurately measured on a continuous basis.

13. The follow up system of claim 12 wherein said struc­ture consists of a photoresist pattern formed upon a polysilicon.

14. The follow up system of claim 13 wherein the said selected wavelength corresponds to the shortest a CO line that is available in the glow discharge.

15. The follow-up system of claim 14 wherein λ= 309,8 nm.

16. A method for detecting an intermediate end point in the dry etching of a structure consisting of a pat­tern formed on a layer when the desired lateral-­dimension reduction of said pattern is attained; said method being characterized in that it comprises the steps of:
- exposing the said pattern to an etching medium within an etching chamber;
- selecting a characteristic wavelength of a species produced in the glow discharge;
- observing the selected wavelength at normal incidence of the pattern through a spectrometer;
- continuously monitoring the vertical dimension reduction by measuring the etched thickness (dTH);
- correlating the corresponding lateral dimension reduction (dW);
- terminating the said exposing step when the said lateral dimension reduction has reached the desired value (dWf).

Drawing