Fabrication process for a self-aligned, lightly-doped drain-source trench transistor

Abstract

 A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region (15) in a wafer including an epitaxial layer (12) on a substrate (10). A first, heavily doped drain region and bit line element (18) is formed around the trench on the surface of the well (15) , and a second, lightly-doped drain region (24) is formed proximate to the first drain region (18) and self-aligned to the trench sidewalls. A source region (26) is located beneath the trench, which is filled with polysilicon (32), above which is gate and further polysilicon forming a transfer wordline (33). The gate polysilicon (32) is separated from the trench side walls by a layer (30) of gate oxide insulation. The well region (15) at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.

Description

[0001] The present invention relates to a vertical lightly-­doped drain trench transistor for ROM and DRAM cells and to a method of fabricating the same.

[0002] In U.S. Patent 4,466,178, issued August 21, 1984 to Soclof entitled METHOD OF MAKING EXTREMELY SMALL AREA PNP LATERAL TRANSISTOR BY ANGLED IMPLANT OF DEEP TRENCHES FOLLOWED BY REFILLING THE SAME WITH DI­ELECTRICS, an array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope the substrate within the active region. The P type substrate is double energy arsenic planted through one surface to establish a N region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. P+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy N implanted depth. Drive-in diffusion enlarges the P+ areas for the emitter and collector and oxidation fills the moat insulating regions around the active area.

[0003] The oxide is stripped and the N region enhanced to N+ at the surface, with silox being deposited and opened for metal contacts to the N+ region for the base and the emitter and collector regions. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.

[0004] In U.S. Patent 4,541,001, issued September 10, 1985 to Schutten et al entitled BIDIRECTIONAL POWER FET WITH SUBSTRATE-REFERENCED SHIELD, a bidirectional power FET structure is disclosed with high OFF state voltage blocking capability. A shielding electrode is in­sulated between first and second gate electrode in a notch between laterally spaced source regions and channel regions joined by a common drift region around the bottom of the notch. The shielding electrode is ohmically connected to the substrate containing the common drift region to be at the same potential level thereof and within a single junction drop of a re­spective main electrode across the junction between the respective channel containing region and drift region. The steering diode function for referencing the shielding electrode is performed by junctions already present in the integrated structure, eliminating the need for discrete dedicated steering diodes. The shielding electrode prevents the electric field gradient toward the gate electrode on one side of the notch from inducing depletion in the drift region along the opposite side of the notch. This prevents unwanted inducement of conduction channels in the drift region during the OFF state of the FET.

[0005] In U.S. Patent 4,649,625, issued March 17, 1987 to Lu entitled DYNAMIC MEMORY DEVICE HAVING A SINGLE-CRYSTAL TRANSISTOR ON A TRENCH CAPACITOR STRUCTURE AND A FABRICATION METHOD THEREFOR, dynamic random access memory (DRAM) devices are taught wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical side­walls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

[0006] In U.S. Patent 4,651,184, issued March 17, 1987 to Malhi entitled DRAM CELL AND ARRAY, a DRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. A ground line runs past the transistor gate in the upper portion of the trench down into the lower portion of the trench to form the other capacitor plate.

[0007] In U.S. Patent 4,670,768, issued June 2, 1987 to Sunami et al entitled COMPLEMENTARY MOS INTEGRATED CIRCUITS HAVING VERTICAL CHANNEL FETS, a semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semicon­ductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.

[0008] In U.S. Patent 4,672,410, issued June 9, 1987 to Miura et al entitled SEMICONDUCTOR MEMORY DEVICE WITH TRENCH SURROUNDING EACH MEMORY CELL, discloses a semiconductor device that has memory cells respectively located at intersections of bit and word lines arranged in a matrix form, each of the memory cells being con­stituted by a single insulated gate transistor and a single capacitor. One memory cell is formed in an element formation region defined by each of trenches arranged in a matrix form. The capacitor has an insulating film formed along part of a sidewall surface of a trench formed in at least a direction of thickness of a semiconductor substrate and a con­ductive layer formed along the insulating film. The transistor has a gate insulating film adjacent to the capacitor and formed along a remaining portion of the sidewall surface of the trench, a gate electrode formed along the gate insulating film and a diffusion region formed in a major surface of the semiconductor substrate which is adjacent to the gate insulating film. The semiconductor memory device further has an isolation region between two adjacent ones of the memory cells along two adjacent ones of the bit or word lines. A method of manufacturing the semicon­ductor is also proposed.

[0009] In U.S. Patent 4,673,962, issued June 16, 1987 to Chatterjee et al entitled VERTICAL DRAM CELL AND METHOD, DRAM cells and arrays of cells on a semicon­ductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trench sidewalls with word lines and bit lines crossing over the cells.

[0010] In. U. S. Patent 4,683,486, issued July 28, 1987 to Chatterjee entitled DRAM CELL AND ARRAY, a DRAM cell and array of cells, together with method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel, and drain and one capacitor plate are formed in a layer of material inserted into the trench and insulated from the substrate; the gate and other capacitor plate are formed in the substrate trench sidewall. In preferred embodiment bit lines on the substrate surface connect to the inserted layer, and word lines on the substrate surface are formed as diffusions in the substrate which also form the gate. The trenches and cells are formed in the crossings of bit lines and word lines; the bit lines and word lines form perpendicular sets of parallel lines.

[0011] In U.S. Patent 4,683,643, issued August 4, 1987 to Nakajima et al entitled METHOD OF MANUFACTURING A VERTICAL MOSFET WITH SINGLE SURFACE ELECTRODES, a vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor sub­strate, a first conductive layer formed in a pre­determined region including a sidewall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.

[0012] In U.S. Patent 4,728,623, issued March 1, 1988 to Lu et al entitled A FABRICATION METHOD FOR FORMING A SELF-ALIGNED CONTACT WINDOW AND CONNECTION IN AN EPITAXIAL LAYER AND DEVICE STRUCTURES EMPLOYING THE METHOD, a fabrication process for providing an epi­taxial layer on a silicon substrate and over pre­defined insulator-capped islands which forms a self-aligned contact window in the epitaxial layer.

[0013] Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor formed in mono­crystalline silicon stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.

[0014] Attention is also directed to Japanese Patent 58-3287 issued October 1, 1983 to Yuuji Furumura entitled VERTICAL CYLINDRICAL MOS FIELD EFFECT TRANSISTOR and IBM Technical Disclosure Bulletin publication appearing in Vol. 23, No. 9, Feb. 1981 at page 4052, "Reduced Bit Line Capacitance in VMOS Devices" by D. M. Kenney and Vol. 29, No. 5, October 1986 at page 2335, "High Density Vertical Dram Cell."

[0015] An object of the present invention is to provide an improved trench transistor including a lightly-doped drain/source (LDD) region.

[0016] Another object of the present invention is to provide an improved trench transistor structure to improve the electrical breakdown, short-channel effects and reliability.

[0017] Another object of the present invention is to provide an improved fabrication process for providing a method to adjust (or control) the threshold voltage of trench transistor by using oblique angle ion implantation or electron cyclotron resonant (ECR) surface doping technique.

[0018] A further object of the present invention is to provide an improved performance for ROM and DRAM cells wherein the trench transistor with lightly-doped drain/source region is disposed in a cross-point at the crossing of a word line and bit line.

[0019] One way of carrying out the invention is described in detail below with reference to drawings in which:

Fig. 1 is a side cross-sectional illustration of an embodiment of a trench transistor according to the present invention.

Fig. 2 is a plan view of a schematic illustration of the trench transistor of Fig. 1.

Figs. 3 through 12 are side cross-sectional illus­trations of the trench transistor of Fig. 1 in various stages of the fabrication process of the present invention.

Fig. 13 is a schematic illustration of the trench transistor devices of Figs. 1 and 12 em­ployed as a ROM cell connected between word and bit lines in a memory array.

Figs. 14 and 15 are schematic illustrations of the trench transistor device of the present invention employed as DRAM cells.

[0020] A new fabrication process is described for a novel cross-point lightly-doped drain/source (LDD) trench transistor. The cross section of this new vertical transistor is shown in Fig. 1 together with a plan view of its schematic layout shown in Fig. 2. The trench transistor is built on the surface of a U-groove. The U-groove shallow trench transistor is designed to be disposed in a cross-point at the crossing of a wordline and a bit line of a memory. The layout of this transistor provides the advantages of ultra small size, high packing density, and faster performance.

[0021] The applications of the trench transistor of the present invention to ROM and DRAM cells are also described.

[0022] The novel fabrication process for the self-aligned, lightly-doped drain/source (LDD) n-channel field-ef­fect trench transistors are described in the following steps.

Step (1) Start with a wafer with n- epi layer 12 on n+ substrate 10, pattern and form pad oxide and silicon nitride layers, define and ion-implant boron to form a retrograde p-well region 15 as shown in Fig. 3.

Step (2) Form pad oxide, define the shallow oxide isolation trench regions 16. Then implant phosphorous to form n++ diffusion region 18. This region 18 will be formed as drain junctions of the resultant access transistors and will also extend to serve as diffusion bit lines 19 as shown in Fig. 2.

Step (3) Form pad oxide, define and etch shallow trench 20 using RIE to form vertical access transistor region as shown in Fig. 5. The depth of this shallow trench is designed to be located either inside or outside the p-well region 15, depending on the ap­plications.

Step (4) Perform p+ doping at the sidewall of the trench to control the n-channel threshold voltage by using the oblique ion implantation technique or electron cycletron resonant (ECR) surface doping technique as shown in Fig. 6. The ion incident angle is adjusted according to aspect ratio of the groove. This step 6 is not mandatory.

Step (5) Form pad oxide and silicon nitride layers. Then use proper highly selective etching (slightly overetching) to form silicon nitride sidewall spacer 22 at the sidewalls of shallow trench as shown in Fig. 7.

Step (6) Form self-aligned and lightly-doped drain (LDD) like n+ junction 24 and buried n+ source junction 26 simultaneously by the low angle oblique ion implantation technique as shown in Fig. 8.

Step (7) As shown in Fig. 9, grow the thicker oxide region 16A wherein the thickness is greater than that of the gate oxide.

Step (8) Remove the silicon nitride sidewall spacer 22 by selective etching. Then grow a thin gate oxide layer 30 on the vertical walls at the shallow trench and on the other area as shown in Fig. 10.

Step (9) Fill shallow trench with CVD n+ polysilicon and pattern to form the transfer gate 32 and word line 33. Deposit metal, react to form silicide. The rest of the fabrication processes are kept the same as standard CMOS technology to complete the transistor structure of Fig. 11. The final cross section of the trench cell is shown in Fig. 1.

[0023] The first example of an application of the LDD trench transistor to a cell array of a cross point ROM cell is shown in Fig. 12. For example, a 14-bit input address code, results in 2¹⁴ = 16,384 word lines, with 4 bits per output address code. The memory array for this system consists of 16,384 x 4 (64K) inter­sections, as indicated schematically in Fig. 13. This address code conversion to be performed by ROM is permanently programmed during the fabrication process by using a custom-designed BEOL mask so as to con­struct or omit a trench at each array intersection. Such an array is indicated in Fig. 13, which shows how the memory FETs are connected between word and bit lines. This arrangement is different from the con­ventional ROM array which is programmed at each bit line. Also, using the n+ diffusion bit lines as interconnections leads to the advantage of reduced drain contact area. Furthermore, the source and drain are vertically isolated, so that there is no need for an isolation region in the cell array. A 3.6 µm² cell is achievable using 0.7 µm technology. This corresponds to the cell size of 16 Mb ROMs.

[0024] The LDD trench transistor of the present invention can also be used with DRAM cell arrays to improve the DRAM cell performance. As mentioned before, by adding the nitride sidewall spacer and oblique angle ion-im­plantation process steps, new LDD access trench transistor can be incorporated into the prior art cross-point DRAM cells which are shown in Figs. 14 and 15, respectively, wherein the n-channel LDD trench transistor of the present invention is used instead of the conventional p-channel trench transistor.

[0025] What has been described is a novel fabrication process to fabricate a unique LDD trench transistor structure.

[0026] By using the nitride sidewall spacer technique, the thicker oxide over drain and source junctions are grown simultaneously. The coupling capacitances between the gate and drain junctions (or the wordline and bit line), and between the gate (WL) and storage node are reduced to a minimum. Hence the access performance of cross-point ROM and DRAM cells will be improved.

[0027] The spacer defined lightly-doped drain (LDD) structure optimizes the vertical transistor. The transistor provides self-aligned source and drain junctions, improved short channel effect, improved punch-through characteristics, lower mobility degradation and reduced overlap capacitance with minimized source and drain incremental resistance.

[0028] The topography of this new structure is flat after gate level; it can be easily enhanced by several additional levels of interconnecting metallurgy. Also the threshold voltage of vertical transistor can be adjusted by using oblique angle ion implantation technique, or electron cycletron resonant (ECR) surface doping technique.

Claims

1. A self-aligned, lightly-doped drain/source field effect trench transistor device comprising:
a substrate (10, 12) of a first conductivity type, the upper portion (12) of said substrate being lightly doped and the lower portion (10) being heavily doped, said upper lightly doped portion being less conductive than said heavily doped lower portion,
a well region (15) disposed in said upper portion (12) of said substrate and having a conductivity type opposite to that of said substrate,
at least one polysilicon filled trench (32) extending from the surface of said well region (15) and into said well region, said trench being electrically isolated from said well region (15) by a layer (30) of gate oxide insulation of the bottom and sidewalls of said trench between the well region (15) and said polysilicon in said trench (32),
a source junction region (26) and a diffusion region forming a first drain junction region (18) disposed in said well region (15), said source junction (26) and first drain junction regions (18) being heavily doped with first conductivity type impurities, said first drain junction region (18) being located on the surface of said well region (15) surrounding said trench and said source junction region (26) being located in said well region (15) beneath the bottom surface of said trench (32),
a second lightly-doped drain junction region (24) in said well region (15) proximate said first drain junction region (18) and being self-aligned with the upper portion of said sidewalls of said trench, and
a polysilicon word line element (33) disposed over said polysilicon filled trench (32).

2. A transistor device according to claim 1 wherein said lower portion (12) of said substrate is n+ conductivity semiconductor material, said lower portion (10) is n- conductivity semiconductor material and said well region (15) is formed with p- type dopants.

3. A transistor device according to claim 1 or 2 wherein said first drain junction region (18) is heavily doped with n++ type dopants and said second drain junction region (24) is lightly doped with n- type dopants.

4. A transistor device according to claim 3 wherein said well region (15) forming said sidewalls of said trench are doped with p+ type dopants to control the n-channel threshold voltage of said transistor device.

5. A transistor device according to anyone of the claims 1 to 4 wherein said diffusion region forming said first drain junction region (18) also forms a bitline element for said transistor device, and wherein said bitline element and said polysilicon wordline element (33) form a cross-point.

6. A process for fabricating the transistor device according to claims 1 to 5 comprising the steps of:

Step 1) on semiconductor substrate material (10) having a layer of epitaxial material (12) there­on, implanting dopants to form a retrograde well region (15) in said epitaxial material,

Step 2) forming oxide isolation regions (16) in the surface of said well region (15) and implant­ing dopants between said isolation regions (16) to form a diffusion region (18) to provide first drain junction regions,

Step 3) etching a vertical trench (20) through said diffusion region (18) into said well region (15),

Step 4) implanting dopants into the vertical sides of said trench (20) using a low angle oblique ion implantation technique,

Step 5) forming layers of silicon nitride masking material on the vertical sidewalls of said trench (20) extending below the level of said diffusion region (18) formed in Step 2,

Step 6) forming self-aligned and lightly doped second drain junction regions (24) on the side­walls of said vertical trench (20) above said silicon nitride mask layers (22) and form buried source junction (26) below the bottom of said trench (20) by using said low angle oblique ion implantation technique,

Step 7) growing oxide (16A) on said recessed oxide regions and on the bottom of said trench (20) over said source junction (26),

Step 8) removing said silicon nitride mask layer (22) from said vertical trench sidewalls and growing a thin gate oxide (30) on said vertical trench sidewalls, and

Step 9) filling said trench (20) with polysilicon and depositing polysilicon over said filled trench and over said recessed oxide regions and well surface to form transfer gate (32) and wordline elements (33).

7. A process according to claim 6 wherein in Step 1) said substrate (10) is formed of n+ type semicon­ductor material, said epitaxial layer (12) is formed of n- type semiconductor and said well region (15) is doped with p- type dopants.

8. A process according to claims 6 or 7 wherein in Step 2) said first drain junction diffusion (18) region is heavily doped with n++ type dopants.

9. A process according to anyone of the claims 6 to 8 wherein in Step 6) said lightly-doped second drain junctions (24) are formed with n+ type dopants.

10. A process according to anyone of the claims 6 to 9 wherein said dopants implanted into the vertical sidewalls of said trench (20) in Step 4) are p+ dopants to control the n-channel threshold voltage of said transistor device.

Drawing