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<ep-patent-document id="EP90306519B1" file="EP90306519NWB1.xml" lang="en" country="EP" doc-number="0403287" kind="B1" date-publ="19941005" status="n" dtd-version="ep-patent-document-v1-1">
<SDOBI lang="en"><B000><eptags><B001EP>......DE....FRGB..................................</B001EP><B005EP>J</B005EP><B007EP>DIM360   - Ver 2.5 (21 Aug 1997)
 2100000/1 2100000/2</B007EP></eptags></B000><B100><B110>0403287</B110><B120><B121>EUROPEAN PATENT SPECIFICATION</B121></B120><B130>B1</B130><B140><date>19941005</date></B140><B190>EP</B190></B100><B200><B210>90306519.1</B210><B220><date>19900614</date></B220><B240><B241><date>19920416</date></B241><B242><date>19930712</date></B242></B240><B250>en</B250><B251EP>en</B251EP><B260>en</B260></B200><B300><B310>153748/89</B310><B320><date>19890616</date></B320><B330><ctry>JP</ctry></B330></B300><B400><B405><date>19941005</date><bnum>199440</bnum></B405><B430><date>19901219</date><bnum>199051</bnum></B430><B450><date>19941005</date><bnum>199440</bnum></B450><B451EP><date>19931208</date></B451EP></B400><B500><B510><B516>5</B516><B511> 5H 01L  21/00   A</B511><B512> 5B 24B  37/04   B</B512></B510><B540><B541>de</B541><B542>Verfahren zum Polieren von Halbleiterplättchen</B542><B541>en</B541><B542>Method of polishing semiconductor wafer</B542><B541>fr</B541><B542>Procédé de polissage de plaquettes semi-conductrices</B542></B540><B560><B561><text>FR-A- 2 521 895</text></B561><B561><text>JP-A- 6 471 663</text></B561><B561><text>US-A- 2 979 868</text></B561><B561><text>US-A- 3 559 346</text></B561><B561><text>US-A- 4 165 584</text></B561><B562><text>SOVIET INVENTIONS ILLUSTRATED, Sections P/Q, week 8544, 11 December 1985, Derwent Publications Ltd., London, GB.</text></B562><B562><text>PATENT ABSTRACTS OF JAPAN vol. 13, no. 244 (M-834)(3592) 07 June 1989 ; &amp; JP-A-1 051 268; &amp; JP-A-64 051 268</text></B562></B560></B500><B700><B720><B721><snm>Nakazato, Yasuaki</snm><adr><str>698-23 Jakumaku</str><city>Koushoku-shi,
Nagano-ken</city><ctry>JP</ctry></adr></B721><B721><snm>Ogawara, Hiroo</snm><adr><str>958 Uchibori,
Fusetakada</str><city>Nagano-shi,
Nagano-ken</city><ctry>JP</ctry></adr></B721></B720><B730><B731><snm>SHIN-ETSU HANDOTAI COMPANY LIMITED</snm><iid>00816460</iid><adr><str>4-2, Marunouchi 1-Chome</str><city>Chiyoda-ku
Tokyo</city><ctry>JP</ctry></adr></B731></B730><B740><B741><snm>Perry, Robert Edward</snm><sfx>et al</sfx><iid>00041331</iid><adr><str>GILL JENNINGS &amp; EVERY
Broadgate House
7 Eldon Street</str><city>London EC2M 7LH</city><ctry>GB</ctry></adr></B741></B740></B700><B800><B840><ctry>DE</ctry><ctry>FR</ctry><ctry>GB</ctry></B840><B880><date>19911023</date><bnum>199143</bnum></B880></B800></SDOBI><!-- EPO <DP n="1"> -->
<description id="desc" lang="en">
<heading id="h0001"><b>BACKGROUND OF THE INVENTION</b></heading>
<heading id="h0002">FIELD OF THE INVENTION</heading>
<p id="p0001" num="0001">The present invention relates to a method of polishing semiconductor wafers, more particularly to an effective technique suitable for polishing semiconductor wafers, whose surfaces to be polished are required to be very flat.</p>
<heading id="h0003">DESCRIPTION OF THE RELATED ART</heading>
<p id="p0002" num="0002">The final step of manufacturing semiconductor silicon wafers includes a polishing step for forming a specular surface. This step generally employs a method called the mechanochemical method, which combines mechanical attrition and chemical reaction.</p>
<p id="p0003" num="0003">Fig. 4 shows the main components of a polishing apparatus for polishing one face of a semiconductor wafer. As shown in Figs. 4 and 5, numeral 1 indicates a glass plate. A plurality of semiconductor wafers 2 are bonded with wax to the under surface of the glass plate 1. These semiconductor wafers 2, having undergone processes such as lapping, beveling and etching, are bonded in such a manner that they can be attached or removed. A polishing cloth 3a is firmly held on the surface of a turntable 3, which is positioned under the glass plate 1. Polishing is performed by using the apparatus in the following way. The<!-- EPO <DP n="2"> --> semiconductor wafer 2 contacts the polishing cloth 3a under the pressure of the glass plate 1. At the same time, the turntable 3 rotates to cause the glass plate 1, supporting the semiconductor wafer 2, to rotate so as to bring the semiconductor wafer 2 into contact with the polishing cloth 3a on which polishing slurry is sprayed. As a result, the main surface of the semiconductor wafer 2 bonded to the underface of the glass plate 1 is polished. The polishing slurry is a weak alkaline aqueous solution containing colloidal silica as fine abrasive grains.</p>
<p id="p0004" num="0004">With an increasingly strong demand in recent years for high precision flatness in the semiconductor wafer surface to be polished because of microscopically fine patterns of semiconductor ICs, the following problems have arisen with the above-described polishing method.</p>
<p id="p0005" num="0005">There are more specifically, when the semiconductor wafer is polished by the above-mentioned polishing apparatus, quality changes of the polishing cloth 3a over time, deformation of the glass plate 1 caused by pressure applied when the semiconductor wafer 2 comes in contact with the polishing cloth 3a, and different rotation speeds of the turntable 1 at various positions along the radius of the table 1, take place. Uneven thickness of the polished semiconductor wafer caused by the above cited phenomena cannot be neglected from a view point of<!-- EPO <DP n="3"> --> requirements for semiconductor IC devices' sophistication in recent years.</p>
<p id="p0006" num="0006">The uneven thickness gives much more influence on semiconductor on insulator (SOI)-structured devices having an extremely thin active zone.</p>
<p id="p0007" num="0007">The more the semiconductor wafer 2 is pressed against the polishing cloth 3a, the faster the polishing speed becomes. It is difficult, however, to control the polishing amount with a fast polishing speed. On the contrary, it is easy to control the polishing amount with a slow polishing speed, though polishing is time-consuming.</p>
<p id="p0008" num="0008">US-A-2 979 868 describes a lapping machine for polishing a semiconductor wafer which includes thickness-regulating members. The thickness-regulating members preferably consist of a hard metal. However, contamination may be a problem when using a metal.</p>
<heading id="h0004"><b>SUMMARY OF THE INVENTION</b></heading>
<p id="p0009" num="0009">It is an object of the present invention to overcome the above-described problems in the conventional method, and to provide a method of quickly polishing a semiconductor wafer, which permits easy control of the polishing amount, and which further permits keeping unevenness in thickness of the semiconductor wafer where one surface is the surface to be polished to a minimum.</p>
<p id="p0010" num="0010">In order to achieve the aforesaid object, the present invention discloses a method of polishing a semiconductor wafer according to the single claim. The semiconductor wafer bonded to a plate is polished to a desired thickness by pressing the semiconductor wafer against a rotating turntable side. The<!-- EPO <DP n="4"> --> semiconductor wafer is bonded to the plate, and at the same time, thickness regulating members whose surface layer is made of a material where polishing speed is slower than the semiconductor wafer, are arranged on the plane of the plate in order to control the thickness of the semiconductor wafer.</p>
<p id="p0011" num="0011">According to the present invention, a semiconductor wafer to be polished is bonded to a plate, and at the same time, the thickness regulating members, whose surface layer is made of a material where polishing speed is slower than the semiconductor wafer, are arranged around the bonded semiconductor wafer and closely spaced-apart from it on the plane of the plate. The semiconductor wafer is polished by using the thickness regulating member as a stopper. For these reasons, even if the polishing speed increases under circumstances that the semiconductor wafer is pressed to the turntable at increased pressure, a part of the pressure is to be borne by the thickness regulating member when the polishing is just about finished. As a result, the polishing speed becomes slow according to the increase in the pressure applied to the wafer by the amount of the pressure borne as mentioned above, and thus it is easy to control the polishing amount of the semiconductor wafer as well as the thickness of the semiconductor wafer. The polished surface of the semiconductor wafer thus becomes even in thickness variation<!-- EPO <DP n="5"> --> across and specular.</p>
<p id="p0012" num="0012">Further, since the thickness regulating member, arranged around the semiconductor wafer, acts as a stopper, the semiconductor wafer is so polished that the surface of the thickness regulating member on the turntable side is substantially flush with the semiconductor wafer, thereby contributing to a less uneven thickness across the whole surface of the semiconductor wafer where one surface is the surface to be polished.</p>
<p id="p0013" num="0013">For all the reasons described above, a highly geometrically controlled polished semiconductor wafer can be obtained.</p>
<p id="p0014" num="0014">Other objects and novel features of the present invention will become apparent from the following Detailed Description of the Preferred Embodiment when read together with reference to the accompanying drawings.</p>
<heading id="h0005"><b>BRIEF DESCRIPTION OF THE DRAWINGS</b></heading>
<p id="p0015" num="0015">
<ul id="ul0001" list-style="none">
<li>Fig. 1 is a vertical section showing part of a polishing apparatus utilized in the polishing method of an embodiment according to the present invention;</li>
<li>Fig. 2 is a plan view of a plate illustrating how a semiconductor wafer and dummy wafers (a thickness regulating member) are bonded to the plate;</li>
<li>Fig. 3 is a plan view of the semiconductor showing<!-- EPO <DP n="6"> --> positions to measure the thickness of the semiconductor wafer according to an experiment;</li>
<li>Fig. 4 is a vertical section showing part of a polishing apparatus used in a conventional method;</li>
<li>Fig. 5 is a plan view of a plate illustrating how the semiconductor wafer is bonded to the plate.</li>
</ul></p>
<heading id="h0006"><b>DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS</b></heading>
<p id="p0016" num="0016">An embodiment of the method of polishing a semiconductor wafer according to the present invention will be described below.</p>
<p id="p0017" num="0017">Fig. 1 shows the major components of a polishing apparatus for polishing one face of the semiconductor wafer.</p>
<p id="p0018" num="0018">As shown in Figs. 1 and 2, one semiconductor wafer 12, having undergone processes such as lapping, beveling and etching, is bonded with wax to the central under surface of the glass plate 11. Moreover, a total of eight dummy wafers 15, serving as thickness regulating members, are so arranged on the under surface of the glass plate 11 as to encircle the above semiconductor wafer 12. When the semiconductor wafer 12 and the dummy wafers 15 are bonded with wax to the surface of the glass plate 11, it is desirable to control bonding gaps by the precision less than 0̸.1 µm, to meet the severest demands. Either of the following two methods allows such a control: the semiconductor wafer 12 is bonded to the surface of the glass plate 11 after molten wax is<!-- EPO <DP n="7"> --> uniformly sprayed in very fine particles by a sprayer on the surface of the wafer 12 to be bonded; or the semiconductor wafer 12 and the dummy wafers 15 are heated after being just placed on the surface of the glass plate 11, and then the wax is introduced to the gaps under the wafers having been melted at a point of the periphery already warmed up before the semiconductor wafer 12 and the dummy wafers 15 are pressed and cooled to fix in order to decrease the gaps and thus clear the severest precision of less than 0̸.1 µm.</p>
<p id="p0019" num="0019">The surface layers of the dummy wafers 15 are made of a material slower to polish than the semiconductor wafer 12. According to the invention, the matrix of the dummy wafer 15 is made of silicon and a silicon oxide or silicon nitride film is formed on the surface layer of the dummy wafer 15. The silicon oxide film may be a thermal oxide film or an oxide film obtained by chemical vapor deposition method (CVD) and is preferably a thermal oxide film, which is slower to remove in polishing by the mechanochemical polishing method. The dummy wafers 15 are bonded with wax to the glass plate 11 in the same manner as in the semiconductor wafer 12, that is, they can be attached or removed, or they are bonded semipermanently with epoxy resin or the like to the glass plate 11. If the dummy wafer 15 is made of a material considerably slower to polish than the semiconductor wafer 12, it is convenient to bond<!-- EPO <DP n="8"> --> the dummy wafer 15 semipermanently to the glass plate 11. When the matrix of the dummy wafer 15 is made of silicon, it is possible to control the thickness of the semiconductor 12 very effectively and accurately.</p>
<p id="p0020" num="0020">A polishing cloth 13a is bonded to the upper surface of the turntable 11 under the glass plate 11.</p>
<p id="p0021" num="0021">Polishing is performed by using the polishing apparatus as follows: the semiconductor wafer 12 contacts the polishing cloth 13a under the pressure of the glass plate 11. At the same time, the turntable 13 rotates to cause the glass plate 11, supporting the semiconductor wafer 12, to rotate so as to bring the semiconductor wafer 12 into contact with the polishing cloth 13a. As a result, the main surface of the semiconductor wafer 12 bonded to the under surface of the glass plate 11 is polished. As an example of a polishing agent, during the polishing operation, colloidal silica, dispersed in an aqueous solution with a pH adjusted to weak alkalinity with NaOH or NH₄OH, is employed. When the semiconductor wafer 12 is polished by the above-described method, the effects described below can be obtained.</p>
<p id="p0022" num="0022">That is, according to the embodiment described above, the semiconductor wafer 12 to be polished is bonded to the central under surface of the glass plate 11, and at the same time, dummy wafers 15, made of a material slower to polish<!-- EPO <DP n="9"> --> than the semiconductor wafer 12, are arranged around the semiconductor 12 under the glass plate 11. For instance, when the matrix of the dummy wafer 15 is made of silicon and a thermal oxide film is formed on its surface layer, the polishing speed for the dummy wafer 15 is, depending upon polishing conditions, 1/20̸0̸ or less of the polishing speed of the silicon.</p>
<p id="p0023" num="0023">Because the semiconductor wafer 12 is polished by using the dummy wafers 15 as a stopper, even if polishing speed increases owing to the condition that the semiconductor wafer 12 is pressed to the turntable 11 under increased pressure, part of the pressure will be borne by the dummy wafers 15 through the whole polishing operation. As a result, the polishing speed slows according to an amount of the pressure shared with the dummy wafers, and thus it is easy to control the polishing amount of the semiconductor wafer 12 as well as the thickness across the whole surface of the semiconductor wafer 12. The polished surface of the semiconductor wafer 12 thus becomes even in thickness across and specular.</p>
<p id="p0024" num="0024">Further, since the dummy wafers 15, arranged around the semiconductor wafer 12, act as a stopper, the semiconductor wafer 12 is so polished that the surfaces of the dummy wafers 15 on the turntable side 11 are substantially flush with the semiconductor wafer 12, thereby contributing to a<!-- EPO <DP n="10"> --> less uneven thickness of the semiconductor wafer 12 where one surface is the surface to be polished. For all the reasons described above, a highly geometrically controlled semiconductor wafer 12 can be obtained.</p>
<p id="p0025" num="0025">The following experiment was performed to confirm the reduced unevenness of thickness of the semiconductor wafer where one surface is the surface to be polished.</p>
<p id="p0026" num="0026">In the experiment, seventeen semiconductor wafers to polish having a diameter of 150̸ mm and, as thickness regulating members, dummy wafers, in a ratio of, for example, four dummy wafers per each semiconductor wafer whose matrix is of silicon and whose surface layer is formed with a silicon oxide film by thermal oxidation, were used.</p>
<p id="p0027" num="0027">As shown in Fig. 3, there are nine positions for measuring the thickness of the semiconductor wafer. We found that it was possible to control very precisely the thickness of the semiconductor wafer according to the experiment. For example, when polished down by about 20̸ µm on the average, the semiconductor wafers whose thickness at a center from the average deviates within ± 0̸.3 µm, comprised 75.8% of the total; the semiconductor wafers whose thickness deviation was 0̸.1 µm or less comprised 50%. The invention has been described in detail with particular reference to the preferred embodiment thereof, but it will be understood that variations and modifications of the<!-- EPO <DP n="11"> --> invention can be made.</p>
<p id="p0028" num="0028">For instance, although as the thickness regulating member, the dummy wafer 15, whose matrix is silicon and with a silicon oxide film formed on its surface layer, is used, a dummy wafer, whose matrix is silicon and with a silicon nitride film formed on its surface layer, can also be used. The shape of the dummy wafer is not necessarily the same as that of the semiconductor wafer. A ring-shaped dummy wafer can be employed so as to encircle the semiconductor wafer 12. The important thing to be considered is<br/>
to use a dummy wafer, which is capable of sharing part of the pressure used to polish the semiconductor wafer on the turntable and which is capable of serving as a stopper.</p>
<p id="p0029" num="0029">Typical effects obtained from the present invention will be briefly described below. When the semiconductor wafer is polished to its desired thickness by pressing it against the rotating turntable side, the semiconductor wafer is bonded to the plate, and at the same time, the thickness regulating member, whose surface layer is made of a material slower to polish than the semiconductor wafer, is<!-- EPO <DP n="12"> --> arranged on the plane of the plate. The thickness regulating member controls the semiconductor wafer thickness. For these reasons, even if the polishing speed increases, it becomes easy to control the polishing amount of the semiconductor wafer. Moreover, because when the table axis vibrates or the like the pressure is borne by the thickness regulating member, the semiconductor wafer is not polished to a thinner thickness than the thickness of the thickness regulating member. As a result, the uneven thickness of a semiconductor wafer where one surface is the surface to be polished is reduced and thus a highly geometrically controlled semiconductor wafer can be obtained.</p>
</description><!-- EPO <DP n="13"> -->
<claims id="claims01" lang="en">
<claim id="c-en-01-0001" num="0001">
<claim-text>A method of polishing or grinding a semiconductor wafer (12) to a desired thickness by pressing the semiconductor wafer against a table (13), with relative rotation, and wherein the desired thickness is determined by the provision of a plurality of thickness-regulating members (15) whose surfaces are more resistant to polishing/grinding than the semiconductor wafer, characterised in that the wafer is bonded to the centre of a plate (11), the members (15) are arranged in a matrix around the wafer, and each member is made of silicon with a silicon oxide or silicon nitride film at its surface.</claim-text></claim>
</claims><!-- EPO <DP n="14"> -->
<claims id="claims02" lang="de">
<claim id="c-de-01-0001" num="0001">
<claim-text>Verfahren zum Polieren oder Schleifen einer Halbleiterscheibe (12) auf eine gewünschte Dicke durch Andrücken der Halbleiterscheibe gegen einen Tisch (13) unter Relativdrehung, und bei dem die gewünschte Dicke durch die Bereitstellung einer Mehrzahl von dickeregulierenden Elementen (15) bestimmt wird, deren Oberflächen beständiger als die Halbleiterscheibe gegen Polieren/Schleifen sind, dadurch gekennzeichnet, daß die Scheibe mit der Mitte einer Platte (11) verbunden wird, die Elemente (15) in einer Matrix um die Scheibe herum angeordnet werden und jedes Element aus Silizium mit einem Siliziumoxid- oder Siliziumnitridfilm an seiner Oberfläche hergestellt ist.</claim-text></claim>
</claims><!-- EPO <DP n="15"> -->
<claims id="claims03" lang="fr">
<claim id="c-fr-01-0001" num="0001">
<claim-text>Procédé de polissage ou de meulage d'une plaquette semi-conductrice (12) à une épaisseur désirée en pressant la plaquette semi-conductrice contre une table (13) en rotation relative, procédé dans lequel on détermine l'épaisseur désirée en prévoyant une pluralité d'éléments (15) de régulation de la pression dont les surfaces sont plus résistantes au polissage/meulage que celle de la plaquette semi-conductrice, procédé caractérisé par le fait que la plaquette est fixée au centre d'une plaque (11), que les éléments (15) sont disposés en une matrice autour de la plaquette et que chaque élément est fait de silicium avec, à sa surface, un film d'oxyde de silicium ou de nitrure de silicium.</claim-text></claim>
</claims><!-- EPO <DP n="16"> -->
<drawings id="draw" lang="en">
<figure id="f0001" num=""><img id="if0001" file="imgf0001.tif" wi="130" he="222" img-content="drawing" img-format="tif"/></figure>
<figure id="f0002" num=""><img id="if0002" file="imgf0002.tif" wi="92" he="103" img-content="drawing" img-format="tif"/></figure>
<figure id="f0003" num=""><img id="if0003" file="imgf0003.tif" wi="137" he="222" img-content="drawing" img-format="tif"/></figure>
</drawings>
</ep-patent-document>
