(19)
(11) EP 0 415 366 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
11.03.1992 Bulletin 1992/11

(43) Date of publication A2:
06.03.1991 Bulletin 1991/10

(21) Application number: 90116506.8

(22) Date of filing: 28.08.1990
(51) International Patent Classification (IPC)5: G06F 9/38
(84) Designated Contracting States:
DE FR GB

(30) Priority: 28.08.1989 JP 222057/89

(71) Applicant: NEC CORPORATION
Tokyo (JP)

(72) Inventor:
  • Suzuki, Nariko, c/o NEC Corporation
    Tokyo (JP)

(74) Representative: Glawe, Delfs, Moll & Partner 
Patentanwälte Postfach 26 01 62
80058 München
80058 München (DE)


(56) References cited: : 
   
       


    (54) Microprocessor having predecoder unit and main decoder unit operating in pipeline processing manner


    (57) Microprocessor (100) having an instruction decoding operation that is performed by a predecoder unit (130) and a main de­coder unit (150) which operates in a pipeline manner by pro­viding between those two units a buffer (140) for temporarily storing information from the predecoder unit (130).







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