Circuit for driving a liquid crystal panel

Abstract

 According to the present invention, there is pro­vided a circuit for driving a liquid crystal panel includes a plurality of shift registers (11Aa, 12Aa, ..., 1mAa) connected in cascade on an A array for trans­ferring data in one direction, a plurality of shift registers (11Bc, 12Bc, ..., 1mBc) on a B array for transferring the data transferred from the shift registers (11Aa, 12Aa, ..., 1mAa) in a direction oppo­site to the one direction, and a plurality of circuit blocks (11Ac, 12Ac, ..., 1mAc; 11Bc, 12Bc, ..., 1mBc) on the A and B arrays for temporarily storing the data transferred from the shift registers (11Aa, 12Aa, ...., 1mAa; 11Bc, 12Bc, ..., 1mBc). The circuit blocks (11Ac, 12Ac, ..., 1mAc; 11Bc, 12Bc, ..., 1mBc) include output stages for supplying the data outside a semiconductor chip, and the output stages are constituted of MOS transistors (3A3, 3B3). The MOS transistors of the first circuit block (11Ac) on the A array and the m-th circuit block (1mBc) of the B array, those of the second circuit block (12Ac) on the A array and the (m-1)-th circuit block (1m-1Bc) on the B array, ..., those of the m-th circuit block (1mAc) on the A array and the first circuit block (11Bc) on the B array are symmetrically arranged, respectively. The currents flow through the symmetrical MOS transistors in the same direction.

Description

[0001] The present invention relates to a semiconductor integrated circuit and, more particularly, to a semicon­ductor integrated circuit used in an LSI for driving a liquid crystal panel with a MOS structure and displaying data on the liquid crystal panel.

[0002] A semiconductor integrated circuit for driving a liquid crystal panel generally comprises a group of shift registers for transferring data, a wire for fetching the data transferred from each of the shift registers, and a circuit for receiving the data and out­putting a signal corresponding to the data. Fig. 1 illustrates a circuit which is formed as an LSI. The LSI includes shift registers 151a to 15na, signal fetch wires 151b to 15nb, circuit blocks 151c to 15nc, and signal fetch pads 151d to 15nd.

[0003] When a semiconductor integrated circuit is formed on a chip as an LSI, in order to reduce the size of the chip, the circuit is divided into A and B arrays to fetch output signals from four sides of the chip, as illustrated in Fig. 2. Since the order of arrangement of output pads 151Ad to 15nBd is the same as that of data transfer, data is transferred from left to right in the A array and from right to left in the B array in shift registers 151Aa to 15nBa, as shown in Fig. 2. The circuit blocks supplied with signals from the shift registers have the same block pattern to easily lay out a mask pattern. Circuit blocks 151Ac to 15nAc in the A array and circuit blocks 151Bc to 15nBc in the B array are, therefore, arranged opposite to each other. In Fig. 2, the direction of character "P" of each circuit block corresponds to that of a mask pattern of the cir­cuit block.

[0004] Fig. 3 is a detail view of a right-side part of the circuit shown in Fig. 2. Referring to Fig. 3, shift register 15nAb comprises clocked inverters 17A1 and 17A2 which are connected in cascade, and circuit block l5nAc includes MOS transistor 17A3. Furthermore, shift register 151Ba comprises clocked inverters 17B1 and 17B2 which are connected in cascade, and circuit block 151Bc includes transistor 17B3. The direction of current 17AI of transistor 17A3 of the circuit block in the A array is opposite to that of current 17BI of transistor 17B3 of the circuit block in the B array. Even though tran­sistors 17A3 and 17B3 whose current directions are oppo­site to each other are formed on the same chip, the dispersions of output characteristics of these tran­sistors, due to misalignment of the mask caused in the manufacture process, are different as shown in Fig. 4. In Fig. 4, L denotes output characteristics of tran­sistor 17A3, and M indicates those of transistor 17B3.

[0005] An explanation of misalignment of the patterns of, for example, a diffusion mask and a polysilicon mask will be given as follows. Fig. 5 shows glass mask misa­lignment of source diffusion layer S₁, drain diffusion layer D₁, and gate electrode G₁ of transistor 17A3 and that of source diffusion layer S₂, drain diffusion layer D₂, and gate electrode G₂ of transistor 17B3. The misa­lignment of gate electrode G₁ increases the resistance of source diffusion layer S₁ and decreases that of drain diffusion layer D₁, and the misalignment of gate electrode G₂ decreases the resistance of source dif­fusion layer S₂ and increases that of drain diffusion layer D₂. The increase of resistance of the source diffusion layer is more influential than that of resistance of the drain diffusion layer since a voltage between the gate electrode and source diffusion layer is lowered by not only a variation in value of the resistance but also a drop of voltage of a resistor of the source diffusion layer and a threshold voltage of the transistor is heightened by increase in a voltage between the substrate and source diffusion layer. As the drain voltage and drain current characteristics of the transistors, as shown in Fig. 6, the current of transistor 17A3 whose source resistance increases is smaller than that of transistor 17B3 whose source resistance decreases.

[0006] Fig. 7 illustrates circuit blocks 15nAc and 151Bc including differential amplifiers 15A and 15B, respectively. Differential amplifiers 15A and 15B greatly influence the output characteristics of the cir­cuit blocks. Since, however, the differential ampli­fiers are asymmetric and the currents thereof flow in the directions opposite to each other, they exhibit dif­ferent output characteristics as shown in Fig. 8.

[0007] It is accordingly an object of the present inven­tion to provide a semiconductor integrated circuit for driving a liquid crystal panel in which the output characteristics between elements or circuits are uni­formed to obtain uniform outputs.

[0008] According to an aspect of the present invention, there is provided a semiconductor integrated circuit for driving a liquid crystal panel, comprising: a semicon­ductor chip; a first group of m data transfer means formed on said semiconductor chip, for transferring data in one direction; a second group of m data transfer means formed on said semiconductor chip, for trans­ferring data from said first group of m data transfer means in a direction opposite to said one direction; and first and second groups of m data output means for tem­porarily storing data from said first and second groups of m data transfer means and outputting the data outside said semiconductor chip, wherein circuit elements of a first one of said first group of data output means and an m-th one of said second group of data output means, those of a second one of said first group thereof and a (m-1)th one of said second group thereof, ..., and those of an m-th one of said first group thereof and a first one of said second group thereof have output stages for supplying data outside said semiconductor chip, the cir­cuit elements constituting the output stages have the same function and are symmetrically arranged, and currents flow through the symmetrically-arranged cir­cuits elements in the same direction.

[0009] In the present invention, the transistors of both circuit blocks, which greatly influence the circuit characteristics between the blocks, are symmetrical and the currents thereof flow in the same direction. Even though the dispersion of the characteristics due to mask misalignment occurs in the manufacturing process, the uniform characteristics can be obtained between both the circuit blocks.

[0010] This invention can be more fully understood from the following detailed description when taken in con­junction with the accompanying drawings, in which:

Figs. 1 and 2 are block diagrams illustrating a conventional semiconductor integrated circuit for driving a liquid crystal panel;

Fig. 3 is a circuit diagram illustrating the con­ventional semiconductor integrated circuit;

Fig. 4 is a graph of the electrical characteristics of MOS transistors of the conventional semiconductor integrated circuit;

Fig. 5 is a plan pattern view of the MOS tran­sistors of the conventional semiconductor integrated circuit;

Fig. 6 is a graph of the electrical characteristics of the MOS transistors of the conventional semiconductor integrated circuit;

Fig. 7 is a circuit diagram of the conventional semiconductor integrated circuit using differential amplifiers;

Fig. 8 is a graph of the output characteristics of the differential amplifiers;

Figs. 9 and 10 are block diagrams showing a semi­conductor integrated circuit for driving a liquid crystal panel according to the present invention;

Fig. 11 is a circuit diagram specifically showing shift registers and circuit blocks of the circuit shown in Figs. 9 and 10;

Fig. 12 is a graph of the output characteristics of a MOS transistor at the output stage of the circuit blocks shown in Fig. 11;

Fig. 13 is a circuit diagram specifically showing shift registers and circuit blocks shown in Figs. 9 and 10;

Fig. 14 is a graph of the output characteristics of a differential amplifier at the output stage of the cir­cuit blocks shown in Fig. 13;

Fig. 15 is a pattern plan view of the MOS tran­sistor shown in Fig. 12; and

Fig. 16 is a graph of electrical characteristics of the MOS transistor shown in Fig. 12.

[0011] An embodiment of the present invention will be described with reference to the accompanying drawings.

[0012] Fig. 9 is a block diagram showing a basic arrange­ment of a semiconductor integrated circuit for driving a liquid crystal panel according to the embodiment of the present invention. In Fig. 9, shift registers 11Aa to 1mAa connected in cascade, for transferring data from an LSI for driving a liquid crystal panel to the right and shift registers 11Ba to 1mBa connected in cascade, for transferring the data to the left are arranged so as to turn around a data transfer path. Signal lines 11Ab to 1mAb are arranged between shift registers 11Aa to 1mAa and circuit blocks 11Ac to 1mAc, respectively, to supply data from the shift registers to the circuit blocks. Signal lines 11Bb to 1mBb are formed between shift registers 11Ba to 1mBa and circuit blocks 1Bc to 1mBc, respectively, to supply data from the shift registers to the circuit blocks. Circuit blocks 11Ac to 1mAc and 11Bc to 1mBc include transistors to the gates of which data is input through signal lines 1Ab to 1mAb and 1Bb to 1mBb. In the upper and lower corresponding circuit blocks in Fig. 9, portions of the circuit blocks directly connected to pads, mentioned later, have a sym­metrical structure and the same function, and the current flows through the circuit portions in the same direction. Circuit blocks 11Ac to 1mAc and 11Bc to 1mBc temporarily store data from shift registers 11Aa to 1mAa and 11Ba to 1mBa, respectively.

[0013] Fig. 10 is a block diagram of the semiconductor integrated circuit shown in Fig. 9, which is formed on chip CH. The circuit is divided into two stages of A and B arrays, and pads 21Ad to 2mAd and 21Bd to 2mBd are pulled out of four sides of chip CH. In Fig. 10, symbol IP indicates an input pad.

[0014] Fig. 11 is a circuit diagram specifically showing part 2c of the circuit shown in Fig. 10. The A Array comprises shift register 1mAa including clocked inver­ters 3AI and 3A2, circuit block 1mAc including MOS tran­sistor 3A3 for receiving transfer data, as a gate signal, from shift register 1mAa through signal line 1mAb, and pad 1mAd serving as a terminal for supplying data from circuit block 1mAc outside the chip. The B array comprises shift register 1mBa including clocked inverter 3B1 and 3B2, circuit block 11Bc including MOS transistor 3B3 for receiving transfer data, as a gate signal, from shift register 11Ba through signal line 11Bb, and pad 11Bd serving as a terminal for supplying data from the circuit block outside the chip. Since MOS transistors 3A3 and 3B3 are directly connected to other circuits, each of which constitutes an LSI for driving a liquid crystal panel which is arranged outside the chip, through pads 1mAd and 11Bd, respectively, the MOS transistors greatly influence the characteristics of circuit blocks 1mAc and 11Bc. The plan patterns of MOS transistors 3A3 and 3B3 are sym­metrical, and currents 3AI and 3BI flow in the same direction. Therefore, as shown in Fig. 12, the output characteristics of MOS transistors 3A3 and 3B3 are the same.

[0015] Fig. 13 is a circuit diagram specifically showing another example of part 2c of the circuit shown in Fig. 10. In Fig. 13, reference numerals 15A and 15B denote differential amplifiers, TR1 and TR2 indicate constant current source transistors, C1 and C2 show dynamic storing capacitors, AS1 and AS2 indicate analog switches, and IN1 and IN2 denote inverters. Since differential amplifiers 15A and 15B are directly con­nected to other circuits, each of which constitutes an LSI for driving a liquid crystal panel which is arranged outside the chip, through pads 1mAd and 11Bd, respec­tively, the differential amplifiers greatly influence the characteristics of circuit blocks 1mAc and 11Bc. The plan patterns of differential amplifiers 15A and 15B are symmetrical, and currents 3AI and 3BI flow in the same direction. Even though mask misalignment occurs in manufacturing an LSI for driving a liquid crystal panel, the output characteristics of differential amplifiers 15A and 15B are the same, as shown in Fig. 14.

[0016] Fig. 15 is a plan pattern view of transistors 3A3 and 3B3 shown in Fig. 11 for explaining the effects obtained by symmetrically arranging the MOS transistors. In conventional transistors which are asymmetrically arranged and into which currents flow in different directions, even though they are formed in the same chip, the characteristics of the transistors vary with the misalignment of masks and the angle of ion-implantation for diffusion of an impurity into source and drain regions. If, however, the transistors are symmetrically arranged and the directions of the currents flowing through the transistors are the same, the characteristics of the transistors are uniformed. Even when misalignment occurs between a diffusion mask pattern and a mask pattern of polysilicon gates G₁₁ and G₁₂, source regions S₁₁ and S₁₂ have the same increase in resistance and drains D₁₁ and D₁₂ have the same decrease in resistance, and the currents of transistors 3A3 and 3B3 flow in the same direction. As shown in Fig. 16, therefore, the drain voltage - drain current characteristics of the transistors are the same.

[0017] In MOS transistors 17A3 and 17B3 of the conven­tional semiconductor integrated circuit for driving a liquid crystal panel shown in Fig. 5, their plan pat­terns are asymmetrical, and the area of source region S₁ of MOS transistor 17A3 is in inverse proportion to that of source region S₂ of MOS transistor 17B3. Further, the area of drain regions D₁ of MOS transistor 17A3 is in inverse proportion to that of drain region D₂ of MOS transistor 17B3. The source resistances of MOS tran­sistors 17A3 and 17B3 are in inverse proportion to each other, and the drain resistances the MOS transistors are also in inverse proportion to each other. Hence, the electrical characteristics of the transistors are dif­ferent.

[0018] The differences in area between source regions S₁ and S₂ and between drain regions D₁ and D₂ of MOS tran­sistors 17A3 and 17B3 are caused by the mask misalign­ment in the manufacturing process. The differences are also caused for the following reason. To form the source and drain regions, an impurity diffuse from the surface of a semiconductor substrate at a predeter­mined implantation angle which is shifted from the right angle with the surface of the semiconductor substrate and therefore, a portion where the implantation is intercepted by the gate region is n arrow and the other portion is large. The difference in area causes the electrical characteristics of the transistors to differ from each other.

[0019] As is apparent from Fig. 15, however, the plan pat­terns of MOS transistors 3A3 and 3B3 are symmetrical with respect to line L. The areas of source regions S₁₁ and S₁₂ of both the transistors are proportionate to each other and the areas of drain regions D₁₁ and D₁₂ thereof are proportionate to each other. Accordingly, the source resistances of transistors 3A3 and 3B3 are proportionate to each other and the drain resistances thereof are proportionate to each other.

[0020] Since the plan patterns of MOS transistors 3A3 and 3B3 are symmetrical with respect to line L, even if source regions S₁₁ and S₁₂ and drain regions D₁₁ and D₁₂ are shifted from polysilicon gates G₁₁ and G₁₂, the electrical characteristics of both the transistors are always the same. The drain voltage - drain current characteristics of the transistors are therefore the same, as shown in Fig. 16.

[0021] Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims

1. A circuit for driving a liquid crystal panel, comprising:
a semiconductor chip (CH);
a first group of m data transfer means (11Aa, 12Aa, ..., 1mAa) formed on said semiconductor chip (CH), for transferring data in one direction;
a second group of m data transfer means (11Ba, 12Ba, ..., 1mBa) formed on said semiconductor chip (CH), for transferring data from said first group of m data transfer means (11Aa, 12Aa, ..., 1mAa) in a direction opposite to said one direction; and
first and second groups of m data output means (11Ac, 12Ac, ..., 1mAc; 11Bc, 12Bc, ..., 1mBc) for tem­porarily storing data from said first and second groups of m data transfer means (11Aa, 12Aa, ..., 1mAa; 11Ba, 12Ba, ..., 1mBa) and outputting the data outside said semiconductor chip (CH),
characterized in that circuit elements of a first one (11Ac) of said first group of data output means (11Ac, 12Ac, ..., 1mAc) and an m-th one (1mBc) of said second group of data output means (11Bc, 12Bc, ..., 1mBc), those of a second one (12Ac) of said first group thereof and a (m-1)th one (1m-1Bc) of said second group thereof, ..., and those of an m-th one (1mAc) of said first group thereof and a first one (11Bc) of said second group thereof have output stages for supplying data outside said semiconductor chip (CH), the circuit elements constituting the output stages have the same function and are symmetrically arranged, and currents flow through the symmetrically-arranged circuits ele­ments in the same direction.

2. A circuit according to claim 1, characterized in that said first and second groups of data transfer means (11Aa, 12Aa, ..., 1mAa; 11Ba, 12Ba, ..., 1mBa) comprise m shift registers serving as data transfer means which are connected in cascade, and said data output means (11Ac, 12Ac, ..., 1mAc; 11Bc, 12Bc, ..., 1mBc) constituting said first and second groups of data output means include MOS transistors (3A3, 3B3) to gates of which data is input from said data transfer means.

3. A circuit according to claim 1, characterized in that said circuit elements constituting said first and second groups of data output means (11Ac, 12Ac, ... 1mAc; 11Bc, 12Bc, ..., 1mBc) and serving as output sta­ges for supplying data outside said semiconductor chip (CH) are differential amplifiers (15A, 15B).

Drawing