CRT compatible driver for a matrix addressable flat panel colour display

Abstract

 A driver for a matrix addressable colour display panel (100) in which each column of the display contains pixels of only one colour, and in which red, green and blue pixels of each row are grouped in linear triads. The column circuits for applying control voltage information to the pixels are colour-segregated so that the colour separation of the control voltage information generated by the graphics controller is maintained. The synchronous control voltage information generated by the graphics controller is received triad by triad, making the driver compatible with conventional CRT drivers.

Description

[0001] This invention relates to matrix addressable flat panel display, and more particularly to a driver configuration for directly interfacing display panel with a standard CRT display controller.

[0002] Matrix addressable flat panel displays have become increasingly popular as an alternative to the cathode ray tube (CRT), both for television and display applications. This is particularly so in applications where the display depth is limited, such as in automotive and aerospace display panels.

[0003] However, the transition to matrix addressable flat panel displays has been slowed by the drive signal incompatibility with CRT's. Whereas, a CRT graphics controller supplies the RGB (red, green and blue) colour information in synchronism, colour element by colour element, matrix addressable display drivers typically require sequential access to the colour information. As a result, the controller must be customized to generate additional information, or sophisticated circuitry must be added to the driver for accepting and storing synchronously generated data. Either approach adversely affects both cost and performance of the system.

[0004] An example of a conventional active matrix liquid crystal display and driver is shown in Figure 1, where the display panel and driver circuit elements are designated by the reference numerals 10 and 12, respectively. The display panel 10 comprises an N x M array of red (R), blue (B) and green (G) pixels formed at the intersections of the N laterally extending rows and the M vertically extending columns. In each row, M pixels are arranged in a predefined and uniform colour sequence, RBGRBG etc. In adjacent rows, the pixels are colour shifted in either direction by one column. Consequently, each row and each column contains pixels of all three colours.

[0005] A row-activated thin-film transistor at the intersection of each row and column applies a column-supplied control voltage to the respective pixel to control its intensity whenever the transistor is activated. Thus, the driver 12 includes a row circuit 14 for successively activating the various rows of transistors, and one or more column circuits 16, 18 for storing the appropriate control voltages. In the illustrated embodiment, the column circuit 16 supplies control voltages to the odd numbered columns and the column circuit 18 supplies control voltages to the even numbered columns.

[0006] The row circuit 14 comprises a bank 20 of individual driver circuits connected to the various rows of the display panel 10, and a shift register 22 for successively activating the driver circuits of the bank 20 at a shift frequency determined by the horizontal synchronization signal HSYNC on line 24. A vertical synchronization signal VSYNC on line 26 periodically resets the shift register 22 to the first or top row.

[0007] The column circuits 16, 18 each comprise a driver bank 28, 30 of individual driver circuits connected to the various columns of the display panel 10, and a shift register 32, 34 for receiving and storing parallel format digital control voltage data via lines 36, 38. The control voltage data is entered into the shift register 32, 34 under control of a SHIFT CLOCK signal on line 40; when a full row of data has been entered, the HSYNC signal on line 24 signals the driver bank 28, 30 to latch the shift register data by way of line 42.

[0008] For display purposes, the pixels are divided into (M x N)/3 groups of colour elements or triads, each comprising a red pixel, a green pixel and a blue pixel. The pixels may be grouped linearly, as indicated by the outlined pixels in row 1, or staggered as indicated by the outlined pixels in rows 3 and 4. The red, blue and green pixel control voltage data is supplied to the driver 12 via lines 44, triad by triad. A colour select circuit designated generally by the reference numeral 45 comprises a demultiplexer (select one-of-three) circuit 46 and a serial to parallel shift register 48 operating under the control of a DOTCLOCK signal on line 50 for suitably applying the pixel control voltage data from lines 44 to lines 36 and 38. The data on lines 44 is in serial format and is applied to the input channels of the demultiplexer circuit 46, which presents individual colour data in succession to serial to parallel shift register 48 on line 54. Since the display columns contain different colour elements and all three pixel colours, the order of the data supplied to serial to parallel shift register 48 varies with the triad grouping and the overall display size.

[0009] The present invention is directed to an improved driver for a matrix addressable flat panel display which can be directly interfaced with a conventional CRT graphics controller without increasing the driver complexity.

[0010] To this end, a flat panel display in accordance with the present invention is characterised by the features specified in the characterising portion of claim 1.

[0011] The driver of the present invention is coupled to a display panel of the type depicted in Figure 1, where the pixels are grouped in linear triads as outlined in row 1. In other words, each row of the display panel comprises a repetitive succession of red, green and blue pixels so that any column contains pixels of only one colour.

[0012] The colour-integrated column circuits of the conventional display driver are replaced with colour-segregated column circuits, eliminating the need for the colour select circuitry. Essentially, the colour-segregated column circuits maintain the colour separation of the control voltage information generated by the graphics controller. To this end, the column driver circuits are split into individual shift register and driver banks dedicated to processing the red, blue and green control voltage data for the even and odd columns of the display panel. A simple toggle circuit controls the flow of the information between the circuits corresponding to the even and odd columns.

[0013] The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:-

Figure 1 is a diagram of the above described conventional PRIOR ART matrix addressable flat panel display and drive circuit; and

Figure 2 is a diagram of a driver for a matrix addressable flat panel display according to this invention.

[0014] Figure 2 illustrates the display panel 10 (herein designated 100) and row circuit 14 of Figure 1 in combination with upper and lower column circuits 112 and 114 according to this invention. Thus, the row circuit 14 comprises a bank 20 of individual driver circuits connected to the various rows of the display panel 100, and a shift register 22 for successively activating the driver circuits of the bank 20 at a shift frequency determined by the horizontal sync signal HSYNC on line 24. The vertical sync signal VSYNC on line 26 periodically resets the shift register 22 to row 1. Due to the linear triad configuration, described above in reference to Figure 1, each output line of bank 20 activates all the pixels of the triads residing in the respective row. In other words, no partial triads are activated.

[0015] The column circuits 112, 114 each comprise a bank 130, 132, 134; 136, 138, 140 of red, green and blue driver circuits connected to the various columns of the display panel 100. The red driver bank 130 is connected to the red pixels residing in odd numbered columns, and the red driver bank 136 is connected to the red pixels residing in even numbered columns. Similarly, the green driver bank 132 is connected to the green pixels residing in odd numbered columns, and the green driver bank 138 is connected to the green pixels residing in even numbered columns. Finally, the blue driver bank 134 is connected to the blue pixels residing in odd numbered columns, and the blue driver bank 140 is connected to the blue pixels residing in even numbered columns.

[0016] The red, green and blue driver banks 130 - 140 are connected to respective red, green and blue shift registers 142, 144, 146; 148, 150, 152 which receive and store parallel format digital control voltage data from the red, green and blue serial data lines, designated R, G and B. As with the prior art display/driver of Figure 1, the data is entered into the shift registers 142, 144, 146; 148, 150, 152 one pixel at a time. Here, however, the upper red, green and blue shift registers 142, 144 and 146 only receive control voltage data for the odd numbered panel columns, and the lower red, green and blue shift registers 148, 150 and 152 only receive control voltage data for the even numbered panel columns.

[0017] The control voltage data is distributed between the upper and lower column circuits 112 and 114 by upper and lower flip-flops 154, 156. Both flip-flops 154 and 156 are clocked by the DOTCLOCK signal on line 158, and oscillate at one-half of the DOTCLOCK frequency. Thus, the event triggering logic level transition (rising or falling edge) of flip-flop 154's Q output occurs at the same time as that of flip-flop 156's Q-bar output. Similarly, the event triggering logic level transition (rising or falling edge) of flip-flop 154's Q-bar output occurs at the same time as that of flip-flop 156's Q output. The Q output of flip-flop 154 enables the upper red and blue shift registers 142 and 146 to receive red and blue control voltage data while the Q-bar output enables the upper green shift register 144. The Q-bar output of flip-flop 156 enables the lower red and blue shift registers 148 and 152 to receive red and blue control voltage data while the Q output enables the lower green shift register 150.

[0018] A display-enable signal on line 160 presets the flip-flops 154 and 156 to synchronize their operation with the control voltage data stream on lines R, G and B. Thus, when the first triad (row 1, columns 1-3) of data is generated on lines R, G and B, the red and blue components are directed to upper shift registers 142 and 146, respectively, and the green component is directed to the lower shift register 150. When the second triad (row 1, columns 4-6) of data is generated, the red and blue components are directed to lower shift registers 148 and 152, respectively, and the green component is directed to the upper shift register 144. When the third triad (row 1, columns 7-9) of data is generated, the red and blue components are directed to upper shift registers 142 and 146, respectively, and the green component is directed to the lower green shift register 150, repeating the pattern of the first triad. When the fourth triad (row 1, columns 10-12) of data is generated, the red and blue components are directed to lower shift registers 148 and 152, respectively, and the green component is directed to the upper shift register 144, repeating the pattern of the second triad.

[0019] The above-described data process is continued until the control voltage data for each triad of row 1 is stored in the shift registers 142-152. In particular, the upper red shift register 142 will have stored the R1, R3, R5, R7, etc. data (where the numeral indicates the triad number); the upper green shift register 144 will have stored the G2, G4, G6, G8, etc. data; the upper blue shift register 146 will have stored the B1, B3, B5, B7, etc. data; the lower red shift register 148 will have stored the R2, R4, R6, R8, etc. data; the lower green shift register 150 will have stored the G1, G3, G5, G7, etc. data; and the lower blue shift register 152 will have stored the B2, B4, B6, B8, etc. data. At such time, the horizontal sync signal HSYNC on line 24 directs the (driver) banks 130-140 to latch the data from the respective shift registers 142-152, and the vertical sync signal VSYNC signal on line 26 directs the shift register 22 and bank 20 to activate the row 1 via driver output line 1 to suitable energize the respective pixels of display panel 100. Subsequent horizontal sync pulses HSYNC direct the row shift register 22 to activate successive rows as described above.

[0020] In the above manner, control voltage data for successive rows of pixels is loaded into the shift registers 142-152, latched into the (driver) banks 130-140 and applied to the respective control panel pixels. The colour select circuitry 45 of the prior art display/driver is substantially eliminated since colour separation of the control voltage data is maintained by the drive circuitry.

Claims

1. A flat panel display comprising a display panel (100) including N individually controllable red (R), green (G) and blue (B) pixels disposed in a matrix array of vertically extending columns and laterally extending rows; column driver means (130-140); and row driver means (20); characterised in that the pixels in each row are (1) disposed in each column in a repetitive succession of colours such that the pixels disposed in each column are of the same colour, and (2) grouped to define laterally extending triads of red, green and blue pixels; in that the column driver means (130-140) receives and stores synchronously generated red, green and blue control voltage information for each triad of a given display panel row; and in that the row driver means (20) activates the given display panel row to enable application of the stored control voltage information to the pixels which define the respective triads.

2. A flat panel display as claimed in claim 1, wherein the column driver means comprises red register means (142,148) for receiving and storing the red control voltage information; green register means (144,150) for receiving and storing the green control voltage information; and blue register means (146,152) for receiving and storing the blue control voltage information.

3. A flat panel display as claimed in claim 1, wherein the column driver means comprises first red, green and blue register means (142,144,146) for receiving and storing red, green and blue control voltage information for pixels disposed in odd columns of the display panel (100); second red, green and blue register means (148,150,152) for receiving and storing red, green and blue control voltage information for pixels disposed in even columns of the display panel; and means (154,156) for (1) directing red, green and blue control voltage information corresponding to pixels disposed in the odd columns to the first red, green and blue register means, and (2) directing red, green and blue control voltage information corresponding to pixels disposed in the even columns to the second red, green and blue register means.

Drawing