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(11) | EP 0 425 284 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Non-volatile semiconductor memory device with improved layout |
| (57) A non-volatile semiconductor memory device is fabricated on a semiconductor chip
and comprises a memory cell array (52) having memory cells arranged in rows and columns
and occupying a first area, a row address decoder unit (53) coupled through word lines
(W1 to Wn) to the rows of the memory cells and responsive to row address bits for
shifting one of the word lines to an active level, a column selector unit (55) coupled
through digit lines (D1 to D4) to the columns of the memory cells and occuoying a
second area contiguous to the first area, a sense amplifier unit (56) coupled through
common digit lines (59a to 59d) to the column selector unit and occupying a third
area contiguous to the second area, and a column address decoder unit (54) responsive
to column address bits and coupled through output lines to the column selector unit,
wherein the sense amplifier unit and the column address decoder unit occupy a fourth
area contiguous to the third area so that no rearrangement of the output lines is
necessary for a new device increased in the memory capacity. |