Color translation circuit

Abstract

 Disclosed is a color translation circuit utilizing a monitor circuit to identify and prioritize windows to be displayed in a multi window environment on a screen. Through the use of the monitor circuitry the size of video memory is reduced.

Description

[0001] This invention relates to color palettes for use in conjunction with video display devices, and more particularly to a color translation circuit for use with color palettes.

[0002] Figure 1 illustrates in block diagram form, and in a simplified manner, a typical prior art color palette 1, which may be for example an Advanced Micro Devices model Am 81C458(/45l) color palette available from Advanced Micro Devices, 901 Thompson Place, P.O. Box 3453, Sunnyvale California 94088. Color palette 1 receives video information from video memory 2 over bus 3. The information stored in video memory 2 is arranged in planes and in this embodiment eight planes of memory provide information to color palette 1. Color palette 1 converts the video information which is presented in digital form to analog information to provide red, green and blue output signals to typically a color monitor. In the embodiment illustrated in Figure 1, inputs P0-P7 provide the pixel select information which specifies the color of each pixel for the picture being displayed. The selection of displayable colors is included in lookup table 4 of color palette 1. As is well known in the prior art, lookup table 4 is programmed via bus means, not shown, to provide up to 256 individual addressable locations which may define a unique color at each location. As indicated in Figure 1, lookup table 4 includes 256 individual addressable storage locations which may be either 24 or 12 bits wide. For 24 bit wide addressable locations, 8 bits are used to define the red output, 8 for the green output and 8 for the blue output. Addressing a location in lookup table 4 is achieved by the input on bus 5, which is as indicated in Figure 1 by the "/" through bus 5 is 8 bits wide, which provides the ability to select any one of the 256 locations. In the case of twenty-four bit wide storage locations, when a location in lookup table 4 is addressed, 8 bits of digital information are provided to digital-to-analog converter 6 which converts the digital information from lookup table 4 to an analog signal representative of that color to provide the intensity of the red drive, the output of which is presented on lead 7. Similarly, 8 bits of information are provided from lookup table 4 to the green drive digital-to-analog converter 8, the output of which is presented of line 9; and 8 digital bits of information are provided to digital-to-analog converter 10 which provides the output on line 11 for the blue drive. Color palette 1 includes 5:1 multiplexer 12 which receives information from bus 3 and provides 8 bits of output for each of the five groups of inputs P0-P7 received over bus 3. Although there are 40 lines in bus 3 into color palette 1, the 5:1 multiplexer 12 presents only eight inputs at a time to lookup table 4 so that each pixel is defined by the information contained in the location addressed by the 8 bits presented to lookup table 4 over bus 5.

[0003] Additional inputs to color palette 1 include OVLO, 1 which is provided over bus 13. The OVLO, 1 input provides overlay information to be displayed on a screen. For the purposes of the present invention, this is not relevant and will not be described in detail. However, publications by Advanced Micro Devices provide additional information on this aspect of prior art color palette 1. Bus 14 provides both data and address information over input lines D0-D7 which is utilized for transferring data into and out of chip 1. The data provided over bus 14 is for loading information into and reading information from chip 1, in contrast to the data provided over bus 3 which is utilized solely for addressing locations in lookup table 4.

[0004] With the embodiment illustrated in Figure 1, the eight planes of memory in video memory 2 provide the ability to identify any of the 256 locations in lookup table 4. In many environments such as multiprocessing/multiwindowing, there is a need to provide fewer numbers of colors per window for example and to provide simultaneously a plurality of windows on the screen display. For example, if 32 colors are all that is needed in a particular window, this may be achieved by a 5 bit address to lookup table 4 since 2⁵ provides 32 identifiable separate locations. In the multiwindow environment in the prior art, such as illustrated in Figure 1, 5 bits from video memory 2 are used to identify which of the 32 colors are desired for a pixel and 3 bits are used to indicate which group of 32 locations in lookup table 4 should be used in identifying the 1 out of 32 colors desired for the pixel. Thus for multiwindows with 32 colors in each window, this provides the possibility of eight sets of windows of 32 colors each since there are 256 addressable locations. In the prior art such as illustrated in Figure 1, eight planes of memory are utilized in video memory 2, which is typically implemented in DRAM, for the identification of each pixel. It is desirable, however, to be able to utilize less DRAM in video memory 2 by reducing the number of planes of memory needed in video memory 2 to identify the colors in a pixel for each window, when as indicated above the total number of colors is a fraction of the possible available colors in lookup table 4. In the prior art, three planes of video memory are dedicated to window information, such as the location, and it is desirable to eliminate those three planes in video memory to reduce the cost of a system where the total number of colors for the desired windows are less than the maximum number available in the lookup table.

[0005] We will describe an arrangement to reduce the number of planes of memory required in a video memory when a plurality of regions are to displayed on a screen and the number of colors in each region is fewer than the total available colors in the lookup table of the color palette.

[0006] In accordance with the invention, a color translation circuit for providing electrical signals to a display device utilizing pixels to display information in a first and a second region on the screen of said display device and further using colors selected from first and second groups of colors, said circuit comprising memory means helping M addressable locations for storing digital information representative of displayable colors and supplying digital signals as outputs from said memory means in response to addressing the storage locations, said memory means including a first group of addressable locations for storing color information for said first region a second group of addressable locations for storing color information for said second region and an output for providing digital signals from said addressable locations; monitor circuit means having inputs for receiving pixel position information and an output coupled to said memory means, said monitor circuit means including means for storing information indicative of the boundaries on said screen of said first and second regions and means for comparing pixel position information with the stored region boundary information and providing an output signal to said memory means which identifies the group of addressable locations which includes the address having the color pixel information for the pixel to be displayed when the position of the to be displayed pixel is within one of said regions.

[0007] In accordance with a preferred feature of the invention, the monitor circuit means includes priority circuit means operative to provide to said memory means the identity of the group containing the address of the pixel to be displayed in those areas in which the boundaries of regions overlap.

[0008] Preferably
the color translation circuit further includes converter circuit means coupled to the output of said memory means for converting digital information received from addressed memory locations in said memory means to analog signals.

[0009] Preferably

[0010] the means for storing information indicative of the boundaries of regions comprise registers. Preferably

[0011] the monitor circuit means of the color translation circuit includes first and second registers for storing region boundary locations in a first axis, first and second comparator circuits associated with said first and second registers respectively, said comparators each having a first input coupled to its associated register and a second input for receiving pixel position information for said first axis, said first and second comparator circuit each having an output terminal for providing an output signal, said comparator circuits being programmed such that an output signal is produced by both of said comparator circuits when the pixel position falls between the stored region boundary locations.

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0012] Other objects and advantages of the invention will become apparent from the study of the specification and drawings in which:

[0013] Figure 1 illustrates a color palette of the type known in the prior art;

[0014] Figure 2 illustrates a display having first, second and third windows;

[0015] Figure 3 illustrates in block diagram-form the preferred embodiment of the present invention; and

[0016] Figure 4 illustrates in expanded block diagram form the monitor circuit of Figure 3.

DETAILED DESCRIPTION OF THE INVENTION

[0017] Figure 3 illustrates the color translation circuit of Applicant's invention which provides the ability to display on a CRT screen a plurality of windows or regions, for example 8 windows or regions of color information, with each window having up to 32 unique colors while utilizing only 5 planes of video memory. Prior to describing in detail the circuit and how this is achieved, as a background, reference is directed to Figure 2 in which there is illustrated display screen 20 having outlined thereon three windows or display regions denoted Window followed by "#" and the number 1, 2 or 3. In this figure, window 1 overlaps windows 2 and 3 and has priority of display, which is indicated by the solid lines for the entire boundary of window 1. For purposes of illustration, although not shown on a typical display screen, the portions of windows 2 and 3 which are behind window 1 are illustrated in dashed lines. As an aid to understanding the present invention, the boundaries of windows 1 and 2 have been indicated in X and Y axis nomenclature. More particularly, the left hand boundary of window 1 is indicated by X1_L and the right hand boundary of window 1 in the x axis in indicated by X1_R; in similar fashion, the upper boundary in the Y axis of window 1 is indicated by Y1_H and the lower boundary of window 1 in the Y axis is indicated by Y1_L. Similarly the left and right sides of window 2 are indicated X2_L and X2_R and the Y axis boundaries for window 2 are denoted Y2_H for the high edge of window 2 and Y2_L for the lower edge. Also illustrated in Figure 2 is line 21 extending in the X axis direction from the left hand edge of display screen 20 to the right hand edge. Various points on line 21 will be used to illustrated how the appropriate portion of the lookup table of the present invention is accessed to provide the appropriate color information to display windows 1 and 2 on screen 20. More particularly, referring to Figure 2, point A on line 21 denotes a pixel location in window 2, point B denotes a pixel location along line 21 which falls in a region where window 1 overlaps window 2 and finally point C on line 21 illustrates a pixel location along scan line 21 which falls only within window 1.

[0018] It will be recalled from the discussion above with respect to the prior art illustrated in Figure 1, that to display 8 windows of 32 colors each on a screen required the use of 8 planes of memory in video memory 2. The present invention, an illustrative example of which is illustrated in Figure 3 (which will be described more fully herein after), permits using only 5 planes of memory in video memory 22, while achieving the same capability as prior art circuits.

[0019] Referring to Figure 3, lookup table 24 functions as the memory means for storing color information displayable by the system and includes 256 addressable locations, each 24 bits wide. The present invention is not limited to any particular capacity lookup table and the size illustrated in Figure 3 is merely presented for illustrative purposes. As is true in the prior art, when multiple windows are utilized, certain lesser numbers of total colors than the full capacity of lookup table 24 may be utilized to display information in various screens. The digital information for red, green and blue outputs for each address is loaded into predetermined address locations as desired by the user and for purposes of simplification the bus for loading lookup table 24 and the addressing means are not illustrated in Figure 3. Well known prior art circuitry may be utilized to load lookup table 24 with the color information. Video memory 22 contains the 5 planes of video memory which provides 5 bits of digital data over bus 25 to 5:1 multiplexer 26. The output signals from 5:1 multiplexer 26 are provided over five bit bus 27 which supplies 5 bits of address information to lookup table 24. These 5 bits of address information can define 32 unique colors and may be utilized in conjunction with the output of monitor circuit 23 to address a total of eight groups of 32 locations each, thereby providing up to eight separate windows each having 32 unique color combinations. As is true in the prior art, video memory 22 is used to identify and supply the color for each pixel to be displayed on the display screen and as the scanning circuits move the beam across the face of the tube the combination of the red, green and blue drives define the color for each pixel displayed. The output of monitor circuit 23 over in bus 28, indicated as a 3 line bus by the "/" and 3 adjacent thereto, serves to identify which of the eight addressable groups of addresses in lookup table 24 should be utilized to create the color information for the pixel to be displayed.

[0020] Addressing one of the 256 locations in lookup table 24 provides 24 bits of digital information defining the red, green and blue drive for the pixel to be displayed, and with the circuit illustrated in Figure 3, eight bits of digital data are supplied to digital-to-analog converter 29 in parallel over bus 30 to provide an analog signal on line 31 providing the drive for the red gun, in the case of a CRT drive with color guns. Similarly, digital-to-analog converter 32 receives over bus 33 digital information which is converted by digital-to-analog converter 32 for the green drive; and digital to analog converter 34 receives 8 bits of parallel information over bus 35, providing the analog drive on output line 36 for the blue drive for the pixel to be displayed. The combination of the outputs from line 31 (red), line 37 (green) and line 36 (blue) define the color of the pixel which will be displayed.

[0021] As indicated above, the identity of the appropriate group of addresses from which the pixel is to be selected is determined by monitor circuit 23 and that identity is provided over bus 28 to lookup table 24. Monitor circuit 23 is loaded with appropriate boundary data and priority information over bus 38. As indicated above with respect to Figure 1, for simplification and ease of understanding, the addressing and loading circuitry for monitor circuit 23 is not here described. Any well known addressing and loading scheme used in the prior art would be applicable with loading of monitor circuit 23 and accordingly a detailed description thereof is not necessary for the purposes of the explanation of the present invention. In addition to providing monitor circuit 23 with boundary data and priority input, in the operation of the present color translation circuit, monitor circuit 23 also receives pixel clock information over line 39 and horizontal synchronization information over line 40.

[0022] Monitor circuit 23 is illustrated more fully in Figure 4 and reference to Figure 4 in conjunction with Figure 2 will aid in understanding of the operation of the present invention. As pointed out above, monitor circuit 23 serves to identify the appropriate group of color address locations for displaying up to eight windows of information on a display screen. It will of course be appreciated that monitor circuit 23 could support any number of windows by providing additional circuits, and the present invention is not limited to a window monitor having only an eight-window support capability. To illustrate the operation of present invention, the boundaries of the windows to be displayed on the screen are loaded into monitor circuit 23 and for purposes for illustration line 21 in Figure 2 will be utilized as an aid in understanding the operation of the circuit of the present invention. For example, to display windows 1 and 2 on screen 20 the boundaries of these windows are loaded into monitor circuit 23 under microprocessor control to define the boundaries in the X and Y direction for the displayable windows. More particularly, with respect to window 1, boundary input data is supplied to register/comparator 46 to provide the left hand boundary of window 1 in the X direction (X1_L), and X1_R boundary location is loaded into register/comparator 47, both being provided over line 41 which is connected to boundary and priority data input bus 38. Suitable register/comparator circuits for use in monitor circuit 23 may be constructed using magnitude comparators such as those available from Texas Instruments under the type number SN74AS885, with the number of bits matching the screen resolution requirements. The numerical value loaded into the register portion of register/comparator 46 defines the X1_L location as the pixel count from the left hand edge of screen 20. And similarly, the numerical value loaded into the register portion of register/comparator 47 to denote the X1_R point as the pixel count from the left hand edge of screen 20. With this information in the registers of register/comparator 46 and register/comparator 47, the boundary in the X direction of window 1 is established. To fully define the boundary of window 1 as a region, the line count from the top of screen 20 to upper and lower edges of window 1 are loaded into the registers of register/comparator 48 and 49, respectively. In the Y axis direction, the horizontal synchronization signal provided over line 40 is utilized to indicate the location of the scan line in the Y direction. With the use of counter 50, the position in the Y, or vertical, direction of the scan beam is provided by the number of counts from the top of the screen, the count being provided over line 51 to register/comparator circuits 48-49, 55-56 as well as the other Y boundary register/comparator circuits to provide the position of the scan line in the vertical direction to the register/comparators for the windows displayable on screen 20. To provide the relative numerical location of the beam in the X direction, counter 51 provides the numerical count of pixels from the left hand edge of screen 20 over line 52 to the register/comparator circuits 46-47, 53-54 and to the other X boundary register/comparator circuits to define the reference point of the pixel to be displayed for a scan across screen 20 in the X direction.

[0023] The X axis boundaries of window 2 are loaded into left and right register/comparator circuits, with X2_L loaded into register/comparator 53 and the right hand boundary for window 2 (X2_R) loaded into register/comparator 54. The Y axis boundaries for window 2, Y2_H and Y2_L are loaded into register/comparators 55 and 56 respectively. With the count data loaded into the registers of register/comparators 53-56, the X and Y boundaries of window 2 have been specified and by comparing the count information from counters 50 and 51 with the data loaded into these register/comparators, the position of a pixel within window 2 may be determined and the appropriate group of addresses in lookup table 24 are thereby identified for the selections of colors to be displayed in window 2.

[0024] Also included in monitor circuit 23 is priority encoder 57 which is utilized to appropriately identify the group of addresses in lookup table 24 when there is an overlap of windows or regions, such as is the case for point B on scan line 21 where the pixel to be displayed should be selected from the group of addresses including the colors established for window 1 since window 1 has the higher priority at that location. Priority encoder 57 could conveniently be implemented using well known generally available devices, such as, for example, Texas Instruments type SN74LS148 8-line to 3-line priority encoder, if the number of possible windows per screen is not more than eight. If the number of windows per screen exceeds 8, similar type circuitry could be utilized.

[0025] To illustrate the selection of the group of addresses for point A on scan line 21, the input count provided from counter 51 over line 52 to register/comparators 46 and 47 results in a digital 1 output on lines A3 and A4 out of register/comparator 53 and 54, respectively, since the comparator portion of register/comparator 53 for X2_L, will indicate the count in the X direction is greater than the data count loaded into the register portion of register/comparator 53 and that count is less than the value loaded into the register portion of register/comparator 54 indicating that the pixel at location A is within the X left and X right region of window 2. As indicated in Figure 4 by the "Z" designation in register/comparator 53, a binary "1" will be provided on line A3 when the count on line 52 is greater than or equal to the number loaded into the register section of register/comparator 53. Register/comparator 53 is, as indicated by "≦αµρ¨" sign, a less than or equal to register/comparator and provides a binary "1" output on line A4 when the count on line 52 is less than or equal to the count loaded into the register portion of register/comparator 54. The other register/comparator circuits in Figure 4 are denoted with the same type of designation to indicate their functioning. The pixel at location A is of course also within the upper and lower Y boundary of window 2. The horizontal count for the Y axis, provided over line 51 to the Y axis register/comparators, when compared with the high location of the Y axis, will be a count greater than the heighth number in the register of register/comparator 55, thus yielding a digital 1 on line B3. Similarly, since the heighth count from counter 50 is less than the lower boundary of window 2, a digital 1 will be output on line B4 from register/comparator 56. Thus with all ones input to AND gate 58, a digital 1 is provided on line 59 as an input to priority encoder 57. With a true input on line 59 to priority encoder 57, the preprogrammed group of addresses in lookup table 24 is identified by the output on bus 28 so that the addresses within lookup table 24 which include the color information for the pixels to be displayed within window 2 are then identified. Having identified the group of addresses, the particular address within the group is identified by the five bits of address information provided to lookup table 24 over bus 27.

[0026] In the example of Figure 2 for the pixel at location B on scan line 21, in addition to a binary 1 being provided on line 59 to priority encoder 57, since the pixel at point B is also within window 2, the output from register/comparators 46, 47, 48 and 49 on lines A1, A2, B1 and B2 respectively, is also a digital 1. This provides binary 1 inputs on all lines to AND gate 60, resulting in a binary 1 output on line 61 to priority encoder 57. Window priority information is provided to priority encoder 57 over boundary and priority data input line 38 during system initialization. Priority encoder 57 provides the address selection over bus 28 to lookup table 24 such that the group of addresses which contain the color information for window 1 will be addressed and the color information for the pixel at location B will be provided by the data stored in the address provided to lookup table 24 over bus 27. It will be recalled that the address information provided over bus 27 defines a portion of the total address needed and the output from monitor circuit 23 is also required since it defines the group of applicable addresses.

[0027] Although not illustrated in Figure 4, it will of course be appreciated that the boundaries for window 3 in the X and Y axis will be loaded into four register/comparators in the same manner as set forth above with respect to the boundaries for windows 1 and 2, and the group of address locations in lookup table 24 would be determined in a similar fashion by use of the register/comparators and appropriate AND gate to provide and input to priority encoder 57 resulting in an output over bus 28 to lookup table 24. Monitor circuit 23 described in the illustrative example in Figures 3 and 4 supports up to eight windows, and as indicated in Figure 4, the group of four register/comparators for the eighth window include register/comparator 62 to define the left hand boundary of window 8 in the X direction, register/comparator 63 for defining the right hand boundary in the X direction for window 8, register/comparator 64 to provide the heighth or highest portion of window 8 in the Y direction and register/comparator 65 to define the lowest point in window 8 in the Y direction. It will of course be appreciated that a true output on lines A15, A16, B15, and B16 into AND gate 66 results in a digital 1 output on line 67 which is an input to priority encoder 57.

[0028] From the forgoing it will be appreciated that an improved color translation circuit is provided in which the need for the number of video memory planes is reduced through the use of a monitor circuit and accordingly the cost of a system is also reduced.

[0029] The forgoing is illustrative of one embodiment of the present invention and to those skilled in the art to which this invention relates variations will become apparent without departing from the spirit and scope of the invention. It is of course also understood that the scope of the invention is not determined by the foregoing description, but only by the following claims.

Claims

1. A color translation circuit for providing electrical signals to a display device utilizing pixels to display information in a first and a second region on the screen of said device and further using colors selected from first and second groups of colors, said circuit comprising:

memory means having M addressable locations for storing digital information representative of displayable colors and supplying digital signals as outputs from said memory means in response to addressing the storage locations, said memory means including a first group of addressable locations for storing color information for said first region, a second group of addressable locations for storing color information for said second region and an output for providing digital signals from said addressable locations;

monitor circuit means having inputs for receiving pixel position information and an output coupled to said memory means, said monitor circuit means including means for storing information indicative of the boundaries on said screen of said first and second regions and means for comparing pixel position information with the stored region boundary information and providing an output signal to said memory means which identifies the group of addressable locations which includes the address having the color pixel information for the pixel to be displayed when the position of the to be displayed pixel is within one of said regions.

2. The circuit of Claim 1, wherein said monitor circuit means includes priority circuit means operative to provide to said memory means the identity of the group containing the address of the pixel to be displayed in those areas in which the boundaries of regions overlap.

3. The circuit of Claims 1 or 2, wherein said color translation circuit further includes converter circuit means coupled to the output of said memory means for converting digital information received from addressed memory locations in said memory means to analog signals.

4. The circuit of Claim 1, wherein said means for storing information indicative of the region boundaries comprise registers.

5. The circuit of Claims 1 or 2, wherein said monitor circuit means includes first and second registers for storing region boundary locations in a first axis, first and second comparator circuits associated with said first and second register respectively, said comparators each having a first input coupled to its associated register and a second input for receiving pixel position information for said first axis, said first and second comparator circuits each having an output terminal for providing an output signal, said comparator circuits being programmed such that an output signal is produced by both of said comparator circuits when the pixel position falls between the stored region boundary locations.

Drawing