Microprocessor having internal cache memory

(19)

(11)

EP 0 432 807 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	16.10.1991 Bulletin 1991/42

(43)	Date of publication A2:
	19.06.1991 Bulletin 1991/25

(21)	Application number: 90124477.2

(22)	Date of filing: 17.12.1990

(51)	International Patent Classification (IPC)⁵: G06F 12/08, G06F 11/10

(84)	Designated Contracting States:
	DE FR GB

(30)

Priority:

15.12.1989 JP 326918/89

(71)	Applicant: NEC CORPORATION
	Tokyo (JP)

(72)	Inventors:
	Sato, Yoshikuni, c/o NEC Corporation Minato-ku, Tokyo (JP) Maemura, Kouji, c/o NEC IC Microcomputer System Minato-ku, Tokyo (JP)

(74)	Representative: Glawe, Delfs, Moll & Partner
	Patentanwälte Postfach 26 01 62 80058 München 80058 München (DE)

(56)

References cited: :

(54)	Microprocessor having internal cache memory

(57) A microprocessor is coupled to an external memory so as to receive therefrom an instruction or data for data processing and a parity bit associated to the instruction or data for data processing. The microprocessor internally comprises a data latch for receiving and holding the instruction or data from the external memory, a parity bit latch for receiving and holding the parity bit associated to the instruction or data, a cache memory for receiving and storing the received instruction or data held in the data latch. The cache memory includes a valid bit prepared for each of the received instruction or data in order to indicate validity of the stored instruction or data. The microprocessor also internally comprises a parity control circuit receiving the received instruction or data held in the data latch and the received parity bit held in the parity bit latch for checking validity of the received instruction or data. The parity control circuit operates to activate a valid bit of the cache memory corresponding to the received instruction or data when the result of the checking indicates that the received instruction or data is valid.

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