(57) A decoder has a plurality of outputs (Ro-RN) each associated with a particular output value and is arranged to add together two
binary numbers (A, B) and to select one of said outputs in dependence on the result
of said sum. The decoder comprises a plurality of logic circuits each arranged to
receive respective bits of both first and second binary numbers to be added together
said logic circuits being arranged to provide, for each output value, a respective
result in dependence on the logic states of said bits and on the logic states of respective
bits of binary numbers representing the particular output value of the decoder; and
logic means for determining when a predetermined condition is satisfied by all the
results of the logic circuits associated with an output value of the decoder, whereby
that output value is selected.
In the preferred embodiment, for adding together two n bit numbers, there are n+l
logic circuits (L), each arranged to receive the ith and i-lth bits (Ai, Ai-l, Bi,
Bi-l) of first and second n bit numbers, and each arranged to provide an output in
dependence on the logic states of said bits and on the logic states of the ith and
i-lth bits (Qi, Qi-l) of respective binary numbers which are the ones complement of
binary numbers Ro...RN representing each respective output value of the decoder in accordance with the following
expression:
The predetermined condition is then satisfied when the above expression has a logic
value of ONE.
A plurality of AND gates are associated respectively with the outputs of the decoder
and are each arranged to receive the outputs of the n+l logic circuits for each output
value of the decoder.
The decoder performs addition and decoding in one step.
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