(19)
(11) EP 0 453 158 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
01.04.1992 Bulletin 1992/14

(43) Date of publication A2:
23.10.1991 Bulletin 1991/43

(21) Application number: 91303128.2

(22) Date of filing: 09.04.1991
(51) International Patent Classification (IPC)5: G06G 7/186, G06G 7/184, G11C 27/02
(84) Designated Contracting States:
DE FR GB IT

(30) Priority: 12.04.1990 US 509657

(71) Applicant: Hewlett-Packard Company
Palo Alto, California 94304 (US)

(72) Inventors:
  • Gilsdorf, Michael J.
    Corvallis, OR 97330 (US)
  • Badyal, Rajeev
    Corvallis, OR 97330 (US)

(74) Representative: Colgan, Stephen James et al
CARPMAELS & RANSFORD 43 Bloomsbury Square
London WC1A 2RA
London WC1A 2RA (GB)


(56) References cited: : 
   
       


    (54) Switched-current integrator circuit


    (57) A switched-current integrator circuit (50) employs track-and-hold circuits (52,54) in which the gates of the current mirror FET switches (M1,M2) are connected together to form a common gate node (58) to double the effective holding capacitance. Additionally, the common gate node (58) is coupled to the input terminal (16) through a CMOS switch (62,64) so that parasitic clock feed-through is essentially cancelled to minimize DC offset voltages (V1,V3 in FIG. 4).






    Search report