<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE ep-patent-document PUBLIC "-//EPO//EP PATENT DOCUMENT 1.4//EN" "ep-patent-document-v1-4.dtd"><!-- Disclaimer: This ST.36 XML data has been generated from A2/A1 XML data enriched with the publication date of the A3 document - March 2013 - EPO - Directorate Publication - kbaumeister@epo.org --><ep-patent-document id="EP91304129A3" file="EP91304129NWA3.xml" lang="en" doc-number="0456475" date-publ="19930224" kind="A3" country="EP" status="N" dtd-version="ep-patent-document-v1-4"><SDOBI lang="en"><B000><eptags><B001EP>......DE....FRGB........NL........................</B001EP><B005EP>J</B005EP></eptags></B000><B100><B110>0456475</B110><B120><B121>EUROPEAN PATENT APPLICATION</B121></B120><B130>A3</B130><B140><date>19930224</date></B140><B190>EP</B190></B100><B200><B210>91304129.9</B210><B220><date>19910508</date></B220><B240 /><B250>en</B250><B251EP>en</B251EP><B260>en</B260></B200><B300><B310>522336</B310><B320><date>19900510</date></B320><B330><ctry>US</ctry></B330></B300><B400><B405><date>19930224</date><bnum>199308</bnum></B405><B430><date>19911113</date><bnum>199146</bnum></B430></B400><B500><B510><B516>5</B516><B511> 5G 06F   7/50   A</B511><B512> 5G 06F   7/48   B</B512></B510><B540><B541>de</B541><B542>Programmierbare logische Schaltung</B542><B541>en</B541><B542>Programmable logic device</B542><B541>fr</B541><B542>Dispositif logique programmable</B542></B540><B560 /><B590><B598>006</B598></B590></B500><B700><B710><B711><snm>Xilinx, Inc.</snm><iid>00676881</iid><irf>IJ/PL75634EP</irf><adr><str>2100 Logic Drive</str><city>San Jose,
California 95124-3400</city><ctry>US</ctry></adr></B711></B710><B720><B721><snm>Hsieh, Hung-Cheng</snm><adr><str>583 Loch Lomond Court</str><city>Sunnyvale,
California 94087</city><ctry>US</ctry></adr></B721><B721><snm>Erickson, Charles R.</snm><adr><str>3412 Atwater Court</str><city>Fremont,
California 94536</city><ctry>US</ctry></adr></B721><B721><snm>Carter, William S.</snm><adr><str>3024 Aspen Drive</str><city>Santa Clara,
California 95051</city><ctry>US</ctry></adr></B721><B721><snm>Cheung, Edmond Y.</snm><adr><str>1302 Shelby Creek Lane</str><city>San Jose,
California 95120</city><ctry>US</ctry></adr></B721></B720><B740><B741><snm>Jones, Ian</snm><iid>00032444</iid><adr><str>W.P. THOMPSON &amp; CO.
Celcon House
289-293 High Holborn</str><city>London WC1V 7HU</city><ctry>GB</ctry></adr></B741></B740></B700><B800><B840><ctry>DE</ctry><ctry>FR</ctry><ctry>GB</ctry><ctry>NL</ctry></B840><B880><date>19930224</date><bnum>199308</bnum></B880></B800></SDOBI><abstract id="abst" lang="en"><p id="pa01" num="0001">Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.<img id="ia01" file="imga0001.tif" wi="125" he="142" img-content="drawing" img-format="tif" /></p></abstract><search-report-data id="srep" srep-office="EP" date-produced="" lang=""><doc-page id="srep0001" file="srep0001.tif" type="tif" orientation="portrait" he="297" wi="210" /></search-report-data></ep-patent-document>