(19)
(11) EP 0 457 039 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
06.05.1992 Bulletin 1992/19

(43) Date of publication A2:
21.11.1991 Bulletin 1991/47

(21) Application number: 91105970.7

(22) Date of filing: 15.04.1991
(51) International Patent Classification (IPC)5G09G 1/16, G09G 5/14
(84) Designated Contracting States:
DE FR GB

(30) Priority: 16.05.1990 US 524201

(71) Applicant: International Business Machines Corporation
Armonk, N.Y. 10504 (US)

(72) Inventors:
  • Larky, Steven Philip
    Austin, Texas 78750-3483 (US)
  • Peevers, Alan Wesley
    Peekskill, New York 10566 (US)
  • St. Clair, Joe Christopher
    Round Rock, Texas 78681 (US)

(74) Representative: Schäfer, Wolfgang, Dipl.-Ing. 
IBM Deutschland Informationssysteme GmbH Patentwesen und Urheberrecht
D-70548 Stuttgart
D-70548 Stuttgart (DE)


(56) References cited: : 
   
       


    (54) Pixel-depth converter for a computer video display


    (57) A pixel-depth converter for converting source-pixel data having a source-pixel depth to destination-pixel data having a destination-pixel depth which differs from the source-pixel depth by a user-selectable pixel-depth-conversion scale factor includes a packed-pixel-data depacker circuit, a pixel-data-conversion-table storage circuit and a plurality of conversion-table address-selector multiplexers. The packed-pixel-data depacker circuit receives source-pixel data words from a source-pixel-data memory and transmits the data words depacked-pixel-data-word-component-by-depacked-pixel-data-word-component in accordance with the selected pixel-depth-conversion scale factor. The pixel-data-conversion-table storage circuit stores user-selectable depth-altering pixel-data-conversion data in locations having conversion-table read addresses which are associated with values of depacked-source-pixel-data portions corresponding to the selected pixel-depth-conversion scale factor. The pixel-data-conversion-table storage circuit includes a plurality of independently-operable converted-data-read parallel output ports and a like plurality of associated conversion-table read-address input ports.







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