The present invention relates to an audio apparatus provided with an anti-howl function.

Audio apparatuses provided with an anti-howl system have widely been introduced and among them is an apparatus which has both a pitch converter and a band-rejection filter interposed between a microphone and a loudspeaker, as disclosed in Japanese Patent Application Laid Open No. 60-28399 (1975). As shown in Fig. 1, that apparatus is arranged such that an audio signal from a microphone 1 is supplied via a microphone amplifier 2 to a pitch converter circuit 3. The pitch converter circuit 3 is provided for varying the frequency of an input audio signal. An output signal from the pitch converter circuit 3 is then fed to a band-rejection filter 4 which actually is a comb filter exhibiting a filter effect in which band-rejection center frequencies are allocated at approximately equal intervals as shown in Fig. 2. Then, an output signal from the band-rejection filter 4 is amplified by a power amplifier 5 for activating a is transmitted to the pitch converter 3 where it is varied in frequency response. The audio signal varied in the frequency passes the band-rejection filter 4 and then, supplied through the power amplifier 5 to the loudspeaker 6 where it is turned to an acoustic output. When a portion of the acoustic output is picked up by the microphone 1, a loop causing a howl is established. The frequency of a feedback audio signal derived from an acoustic input is also varied by the pitch converter 3. It is now assumed that the audio signal from the microphone 1, which has a frequency of f_a as shown in Fig. 3A, is converted by the pitch converter 3 to a feedback audio signal having a frequency of f_b (Fig. 3B) after a duration ₇ of traveling once throughout the loop. After another duration of ₇ traveling once more throughout the loop, it is further converted to a re- feedback audio signal having a frequency of f_c (Fig. 3C). If the frequency f_c is identical to a band-rejection center frequency in the band-rejection filter 4, the audio signal of f_c frequency is blocked by the band-rejection filter 4 and thus, howling will be prevented.

For enhancement in the antihowl effect with the prior art audio apparatus provided with such an antihowl system, it is however necessary to have the band-rejection center frequencies allocated at intervals of a smaller distance in the band-rejection filter 4 for rejecting unwanted howl generating signals. A problem then arises that when a distance between the two adjacent band-rejection center frequencies is reduced, the gain of a frequency band between the same becomes attenuated and thus, the quality of a reproduced sound will be degraded.

It is an object of the present invention to provide an audio apparatus capable of eliminating howls without deterioration in the quality of reproduced sounds.

An audio apparatus according to the present invention is provided with an antihowl system for input of audio signals from a microphone, in which at least one notch filter in which the band-rejection center frequency varies with time is provided in a transmission line of the audio signals.

In the drawings :-Fig. 1 is a block diagram showing a prior art audio apparatus provided with an antihowl system;

• Fig. 2 is a characteristic diagram showing a frequency rejection response in the prior art apparatus illustrated in Fig. 1;
• Figs. 3A to 3C are diagrams showing variations of the frequency of an audio signal when a loop is established in the prior art apparatus of Fig. 1;
• Fig. 4 is a block diagram showing one embodiment of the present invention;
• Fig. 5 is a block diagram showing the arrangement of a DSP provided in the apparatus of the present invention portrayed in Fig. 4;
• Fig. 6 is a diagram of an equivalent circuit provided for performing the same function as of the DSP;
• Fig. 7 illustrates a table showing the storage of coefficient data in a RAM of the DSP;
• Fig. 8 shows a table of the band-rejection center frequencies of first to fifth notch filters;
• Fig. 9 is a characteristic diagram showing frequency rejection actions in the first to fifth notch filters; and
• Figs. 10 and 11 are block diagrams showing two more embodiments of the present invention.

Preferred embodiments of the present invention will be described in detail referring to the accompanying drawings.

Fig. 4 illustrates an improved audio apparatus of the present invention in which an output signal from a micro phone 1 is at first fed to a microphone amplifier 2 of which output port is connected to an A/D converter 7. The A/D converter 7 is coupled at output to a DSP (digital signal processor) 9 which is controlled by a microcomputer 10 as will be described later in more detail. The DSP 9 is also coupled at output to a D/A converter 8 where a digital audio signal from the DSP 9 is converted into an analog audio signal. The output of the D/A converter 8 is connected via a power amplifier 5 to a loudspeaker 6 in the same manner as of the prior art.

Fig. 5 schematically illustrates an arrangement of the DSP 9. In operation, a digital signal from the A/D converter 7 is fed to an input interface 13 in the DSP 9. The input interface 13 is coupled to a data bus 14 which in turn is connected to a data memory 12 provided for temporary storage of signal data and also, to one of the two outputs of a multiplier 15. The other output of the multiplier 15 is coupled to a buffer memory 16 provided for storage of coefficient data. The buffer memory 16 is coupled to a coefficient RAM 17 which holds a plurality of coefficient data. In response to a timing signal from a sequence controller 20, described later, one of the coefficient data stored in the RAM 17 is retrieved and transferred to the buffer memory 16 for storage. The coefficient data retained in the buffer memory 16 is then supplied to the multiplier 15. There is also provided an ALU (arithmetic logic unit) 18 for accumulating calculated outputs of the multiplier 15. The ALU 18 has a couple of inputs; one for receiving a calculated output from the multiplier 15 and the other for communicating to the data bus 14. The output of the ALU 18 is coupled to an accumulator 19 which is in turn connected at output to the data bus 14. The data bus 14 is also connected to a memory controller circuit 22 provided for control on writing and reading of data into and from an external memory 21 for producing delay data.

The data bus 14 is further connected to an output interface 23 which delivers a digital audio signal, i.e. the output of the DSP 9, to the D/A converter 7.

The operational timing in the two interfaces 13 and 23, the multiplier 15, the coefficient RAM 17, the ALU 1, the accumulator 19, and the memory controller circuit 22 is controlled by the sequence controller 20 which is driven according to a processing program loaded in a program memory 24 and also, in response to a command from the microcomputer 10. A keyboard 11 is also connected to the microcomputer 10 for providing various commands through manipulation to the same and keyboard entry will direct the microcomputer 10 for control over the writing of coefficient data into RAM 17.

In operation, a microphone signal fed to the A/D converter 7 is converted in each predetermined sampling period into a digital audio signal form and then, transmitted via the interface 13 to the data memory 12 for storage. A coefficient data read out from the RAM 17 is fed to the buffer memory 16 for temporary storage. The sequence controller 20 is then activated for determining the timing of: reading data from the interface 13, transferring data from the data memory 12 to the multiplier 15 selectively, issuing coefficient data from the RAM 17, triggering the multiplication on the multiplier 15 and the summing on the ALU 18, releasing an output from the accumulator 19, issuing data of calculated results from the interface 23, and so on. For example, the appropriate timing for operation allows both coefficient data 0:1 from the buffer memory 16 and data d₁ from the data memory 12 to be simultaneously fed into the multiplier 15 where they are multiplied to α₁ ·d₁. Subsequently, α₁·d₁ is calculated by the ALU 18 to 0+α₁·d₁ which is in turn stored in the accumulator 19.

Similarly, coefficient data a₂ from the buffer memory 16 and data d₂ from the data memory 12 are multiplied in the multiplier 15 to α₂·d₂. The input of a₂'d, is then combined by the ALU 18 with α₁·d₁ fetched from the accumulator 19 to α₁·d₁ + α₂°d₂ which is also stored in the accumulator 19. By repeating this procedure, a sum total from E α_i·d_i is obtained.

For producing a delay data associated with e.g. a reflected sound, corresponding data is read out from the data memory 12 and transmitted via the data bus 14 to the memory controller circuit 22. The memory controller circuit 22 is then activated to write a series of the supplied data into the external memory 21 in sequence so that after completion of the writing, the data can be retrieved in the form of a delay data at the end of a predetermined delay time data interval. The delay data is then fed via the data bus 14 to the data memory 12 for storage and will be ready for use in the foregoing calculation.

The DSP 9 in the audio apparatus of the present invention is also embodied in the form of an equivalent circuit, as shown in Fig. 6, which serves as a secondary IIR filter.

In this filter, a coefficient multiplier 31 and a delay device 32 are coupled in combination to the input terminal which receives an audio data signal. The delay device 32 is then connected at output to another coefficient multiplier 33 and to another delay device 34 which is in turn coupled at output to a further coefficient multiplier 35. The outputs of their respective coefficient multipliers 31, 33, and 35 are all communicated to an adder 36. The adder 36 is then coupled at output to a delay device 37. Similarly, the delay device 37 is connected at output to a coefficient multiplier 38 and also, to another delay device 39. The delay device 39 is coupled at output to another coefficient multiplier 40 and both the coefficient multipliers 38 and 40 are communicated at output to the adder 36.

The delay time of each delay device 32, 34, 37, or 39 is equal to one sampling period. Accordingly, data fed to the multiplier 33 comes one sampling period earlier than that fed to the multiplier 31 and data fed to the multiplier 35 comes two sampling periods earlier than the same.

Simultaneously, similar data inputs are supplied to the multipliers 38 and 40.

Assuming that the multiplier 31 has a coefficient of ao, the multiplier 33 a1, the multiplier 35 a₂, the multiplier 38 bi, and the multiplier 40 b₂, the equivalent circuit acts as a notch filter when ao =a₂ =A, a₁ =-b₁ = B, and b₂ =an arbitrary value. More particularly, the band-rejection center frequency is varied with and thus, defined by A, B, and b₂.

For developing a single notch filter with the use of digital processing, the DSP 9 is actuated in the following manner.

At the first step, input audio signal data d_n is read out from an n-th location in the data memory 12 and simultaneously, the coefficient data a₂ is retrieved from the RAM 17. Both data are transferred to the buffer memory 16 and multiplied in the multiplier 15. The multiplication a₁·d_n is then added to 0 by the ALU 18 at the third step-two steps after the first step. And, the resultant sum is stored in the accumulator 19.

At the second step, signal data d_n-₁ is read out from an (n-1)-th location in the data memory 12 and multiplied by the coefficient data a₁ from the RAM 17 in the multiplier 15. The multiplication a₁·d_n-1 is then added, at the fourth step, by the ALU 18 to a stored value (the sum calculated at the third step) from the accumulator 19 and the resultant sum is also stored in the accumulator 19. At the third step, an input signal data IN is transferred to an (n-2)-th location in the data memory 12 and also, to the multiplier 15 where it is multiplied by the coefficient data ao. The multiplication a₀·IN is added, at the fifth step, by the ALU 18 to a stored value (the sum at the fourth step) from the accumulator 19 and the resultant sum is stored in the accumulator 19.

Similarly, at the fourth step, signal data d_n+2 is read out from an (n + 2)-th location in the data memory 12 and multiplied by the coefficient data b₂ from the RAM 17 in the multiplier 15. The multiplication b₂·d_n+2 is then added, at the sixth step, by the ALU 18 to a stored value (the sum at the fifth step) from the accumulator 19 and the resultant sum is also stored in the accumulator 19. At the fifth step, signal data d_n+1 is read out from an (n+1)-th location in the data memory 12 and multiplied by the coefficient data b₁ from the RAM 17 in the multiplier 15. The multiplication b₁·d_n+1 is then added, at the seventh step, by the ALU 18 to a stored value (the sum calculated at the sixth step) from the accumulator 19 and the resultant sum is also stored as an output data in the accumulator 19.

The coefficient data ao, a₁, a₂, bi, and b₂ have been read from an internal memory (not shown) in the microcomputer 10 and transferred to a predetermined coefficient data area in the RAM 17. The coefficient data area contains a plurality of coefficient data groups; each data group consisting of the coefficient data ao, a₁, a₂, bi, and b₂ and having different values of A and B, in which the data are stored in the order of a₂, a₁, ao, b₂, and b₁ from the first storage location in the address space.

For forming a plurality-namely five (5)-of the (first to fifth) notch filters which are different in the band-rejection center frequency, the coefficient data groups having a₂, a₁, ao, b₂, and b₁ allocated in one group are retrieved and stored in a sequence of F₁, F₂,..., Fs, F₁+ΔF₁, F₂+ΔF₂,..., F₄ +5ΔF₄, and F₅ +5ΔF₅ as shown in Fig. 7. The data groups F₁ to F₅ are provided for determining the band-rejection center frequencies f₁ to f₅ of the first to fifth notch filters respectively. The center frequencies f₁ to f₅ are also designated as reference frequencies, in which f₁<f₂<f₃<f₄<f₅. The data group F₁ +ΔF₁ is prepared for providing a band-rejection center frequency of f₁ +Δf₁ where f₁ is the reference frequency and Δf₁ is a unit frequency shift. The data group F₁ +2ΔF₁ is prepared for providing a band-rejection center frequency of f₁ plus 2xAfi. Similarly, the data groups F₁ +3ΔF₁, F₁ + 4ΔF₁, and F₁ + 5ΔF₁ are adopted for providing band-rejection center frequencies obtained by adding 3×Δf₁, 4×Δf₁, and 5×Δf₁ to f₁ respectively. The other data groups F₂, F₃, F₄, and F₅ are provided for similar purpose. The frequency shifts Df₁, Δf₂, Δf₃, Δf₄, and Δf₅ in a unit time need not be the same and can be determined independently. In the operation of reading, the coefficient data are retrieved from the first location in the address space by a timing signal given from the sequence controller 20; for example, a₂, a₁, ao, b₂, and b₁ of the data group F₁, a₂, a₁, ao, b₂, and b₁ of the data group F₂, and so on in sequence. When the reading of a₂, a₁, ao, b₂, and b₁ of the last data group F₅+5ΔF₅ is completed, a second reading operation will start with the data group F₁ from the first location of the address space.

The coefficient data groups F₁ to F₅ retrieved are then multiplied by sampling signal data of the first timing respectively and F₁ +ΔF₁ to F₅ +ΔF₅ are multiplied by sampling signal data of the second timing respectively. In similar manner, the coefficient data groups F₁+2ΔF₁ to F₅+2ΔF₅, F₁ +3ΔF₁ to F₅ + 3Δ₅, F₁ +4ΔF₁ to F₅ + 4AFs, and F₁+5ΔF₁ to F₅+5ΔF₅ are multiplied and these steps will be repeated.

Accordingly, the band-rejection center frequencies of the first to fifth notch filters are determined, as shown in Fig. 8, f₁ to f₅ for the coefficient data groups F₁ to F₅ respectively, f₁ +Δf₁ to f₅ +Δf₅ for F₁ + ΔF₁ to F₅ + ΔF₅, f₁ + 2Δf₁ to f₅ + 2Δf₅ for F₁ + 2ΔF₁ to F₅ + 2ΔF₅ , f₁ + 3Δf₁ to f₅ + 3Δf₅ for F₁ + 3ΔF₁ to F₅ + 3ΔF₅, f₁ + 4Δf₁ to f₅ + 4Δf₅ for F₁ + 4ΔF₁ to F₅ + 4AFs, and f₁ + 5Δf₁ to f₅ + 5Δf₅ for F₁+5ΔF₁ to F₅+5ΔF₅. As this procedure is repeated, the band-rejection center frequency of each notch filter will vary with time. For example, the first notch filter shifts the band-rejection center frequency from f₁ which is the reference frequency denoted by the numeral 1 to f₁ +Δf₁ denoted by 2, to f₁ + 2Afi denoted by 3, to f₁ + 3Afi denoted by 4, to f₁ + 4Δf₁ denoted by 5, and to f₁ + 5Afi denoted by 6, as shown in Fig. 9. Like the first notch filter, the second to fifth notch filters change with time their respective band-rejection center frequencies f₂, f₃, f₄, and fs, shown in Fig. 9, in the same manner.

In the aforementioned embodiment, the first to fifth notch filters are intended to be not always equal in the size of frequency shift. It is a common practice in a particular range (namely 1 kHz to 4 kHz) of frequencies which involves more howls to provide an increased number of notch filters as compared with the other band of frequencies, in which the frequency shift of a band-rejection center frequency may be minimized and also, the shifting speed per unit time may be increased. It is preferred that for example, the shift of the band-rejection center frequency ranging from 1 kHz and 4 kHz is 2 Hz and the shifting speed is 1 Hz per unit time.

Although the DSP 9 is chiefly provided in the arrangement of the embodiment according to the present invention, it may be replaced with another device(s). For example, a plurality of notch filters of secondary IIR type 41₁, 41₂,..., 41 _n may be interposed between the A/D converter 7 and the D/A converter 8 as shown in Fig. 10. Each of the notch filters 41₁, 41₂,..., 41 _n which are different in the band-rejection center frequency is arranged so that its band-rejection center frequency is varied by changing a coefficient for multiplication with the controller circuit 42. Those notch filters may also be arranged for constituting an analog circuit.

Fig. 11 illustrates another embodiment of the present invention in the form of an audio apparatus which is constructed by adding a frequency modulation circuit 43 to the arrangement portrayed in Fig. 10. The frequency modulation circuit 43 is provided with a memory (not shown) for varying the frequency of a digital audio signal by writing the signal into the memory and reading it out from the same at a different speed from the writing speed. The frequency modulation circuit 43 is well known, for example, as a tone controller disclosed in Japanese Patent Application Laid-Open No. 61-118797(1986) or 61-121096(1986). So, the details of the circuit will not be described. Such a frequency modulation circuit may be formed with the DSP, in which the writing and reading of data into and from the external RAM 21 shown in Fig. 5 is controlled by the memory controller circuit 22. Also, the frequency modulation circuit may incorporate a known analog circuit. As above described, the audio apparatus provided with an antihowl system according to the present invention has notch filters arranged across the transmission line of an audio signal from a microphone for varying with time the band-rejection center frequency. Accordingly, the notch filters having different band-rejection center frequencies can closely be aligned throughout a particular band of frequencies which tends to cause formidable howls and thus, block unwanted audio signals which are bound to develop a loop causing a howl. Consequently, howls will be eliminated without deterioration in the quality of a reproduced sound.