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(11) | EP 0 474 366 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Graphics display system including a video random access memory with a split serial register and a run counter |
| (57) A graphics system includes a random access memory (105) with a split serial register
(109) having low and high halves of a plurality of storage elements, an access start
point address register (137), and an arrangement (140, 142, 145) for stopping an access
run at the end of a predetermined run length. Thus, there are specified both start
and stop point addresses for a read data access operation from the split serial register
in a graphics processing system. By using these start and stop point addresses, the
operating speed of the graphics processing system is increased. The random access
memory also includes a multiplexer (160) for coupling a column of storage cells from
the memory array to storage elements of the split serial register (109). Data stored
in either a low half or a high half of the addresses of the memory array may be selectively
coupled through the multiplexer to either a low half or a high half of the split serial
register. For a tile oriented graphics display operation, this arrangement increases
the number of choices of where within the random access memory array to store specific
bits of the tile data to be displayed. Data representing a tile can be mapped into
a single row of the random access memory array. |