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(11) | EP 0 477 582 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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Digital frequency multiplication and data serialization circuits Digitale Frequenzmultiplikation und Datenserialisierungsschaltkreis Multiplication digitale de la fréquence et circuit pour la conversion en données sérielles |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
[0001] This invention relates in general to communication systems and information and data processing systems, and more particularly, to digital clock frequency multiplication and data serialization techniques for converting a stream of Q parallel data bits into serial data for transmission and/or processing.
[0002] In optical fiber transmission systems the trend is to increase the data rate further to exploit the high transmission capacity of single- mode optical fibers. The limiting factor for data rate increases is usually not the optical fiber data carrying capability, but rather electronic circuit performance. In digital communication networks, such as fiber optic transmission systems, parallel data bits must be converted into a serial data stream at the transmitting end for transfer to a remote receiving end. Conversion of parallel data to serial data conventionally requires frequency multiplication of the parallel data clock. This is typically accomplished by a phase locked loop (PLL), which is an analog component well known in the art. Data serialization is normally accomplished via a special circuit called a serializer. The PLL and serializer are considered to be critical components of the data communication network. These circuits traditionally operate at the serial data stream rate and usually limit communication channel data carrying capability.
[0003] Such a serializer for example is known from EP 0 346 896 A2. The input data are multiplexed by a frequency in order that the signal on an output line serially represent the parallel bits.
[0004] This principle is also applied for a conventional multiplication and data serialization circuit, generally denoted 10, as depicted in Figure 1. Circuit 10 receives the parallel data clock (low frequency clock) on line 11 which is coupled to a PLL circuit 12. PLL 12 multiplies the parallel clock frequency and outputs on line 13 a serial data clock (high frequency clock) that is phase synchronized with the parallel data clock. The high frequency clock output of PLL 12 is input to a ring counter 14 and the clock "C" input of a data latch 18. Ring counter 14 produces Q synchronized pulses CLC(1), CLC(2), ..., CLC(Q), wherein Q equals the number of parallel data bits. These synchronized pulses are output from counter 14 on respective lines 15 to a data selector 16, which uses the pulses as clocks for the parallel data bits which are input to data selector 16 on lines 17. A clock pulse on a line 15 causes a corresponding data bit on a line 17 to be transferred from a parallel data latch in selector 16 to the serial output stream on line 19. . Line 19 is coupled to the data "D" input of latch 18, which again is clocked by the serial data clock from the PLL 12.
[0005] A phase locked loop typically includes a voltage controlled oscillator, phase detector, charge pump and filter. The voltage controlled oscillator's frequency is normally susceptible to noise, which manifests itself as jitter at the PLL output. Serial data jitter obviously degrades optical link performance and is therefore undesirable. With conventional technology difficulties are experienced in maintaining PLL jitter low in a noisy system environment. In addition, the ring counter and data select circuit of the prior art serializer of Figure 1 consist of a large number of latches which must operate at a high frequency. These components therefore further limit the maximum serial data rate for a particular technology. Also, because of the large number of circuits required, power consumption makes large scale integration difficult.
[0006] As example for a circuit of the standard type the DE-OS 1 815 308 discloses a binary counter, the output thereof being coupled to inputs of gates, also providing an input of a parallel data structure. The outputs of the gates are fed to a common line that receives the serial data. The logic implemented for the different gates allows to switch only that bit of the parallel data structure to the output, that is selected by the appropriate counter output. This circuit therefore is limited in speed by the switching behavior of the gates as well as the counters.
[0007] The present invention is directed to the problem of solving the performance limitations of frequency multiplication and data serialization technology to allow for higher data rate signal processing for a given technology.
[0008] The problem is solved by the method and circuit of the independent claim. Improvements are featured in further claims dependent thereon.
[0009] In a principal aspect, the present invention provides a novel technique for the simultaneous clock frequency multiplication and data serialization of parallel data. The digital techniques described herein accomplish clock frequency multiplication with less jitter than conventional approaches using PLL circuitry. In addition, the present data serialization circuits do not require latches, and are therefore simpler to implement than existing approaches, and can serialize data at a higher rate with less power consumption than conventional techniques, i.e., assuming the same technology and circuit speed.
[0010] These and other objects, advantages and features of the present invention will be more readily understood from the follow detailed description of certain preferred embodiments of the present invention, when considered in conjunction with the accompanying drawings in which:
- Figure 1
- is a block diagram representation of a prior art frequency multiplication and data serialization circuit;
- Figure 2
- is a block diagram representation of a frequency multiplication and synchronization circuit explaining the principle of the present invention;
- Figure 3
- is a block diagram representation of one embodiment of an edge detector useful in implementing the circuit of Figure 2;
- Figure 4
- is a timing diagram for the frequency multiplication and synchronization circuit of Figure 2;
- Figure 5
- is a block diagram representation of one embodiment of a combination frequency multiplication and return-to-zero data serialization circuit pursuant to the present invention;
- Figure 6
- is a timing diagram for the return-to-zero data serialization circuit of Figure 5;
- Figure 7
- is a block diagram representation of one embodiment of a combination frequency multiplication and nonreturn-to-zero data serialization circuit pursuant to the present invention; and
- Figure 8
- is a timing diagram for the nonreturn-to-zero data serialization circuit of Figure 7.
[0011] Referring to Figure 2, one aspect of the present invention is the provision of a digital clock frequency multiplication and synchronization circuit, generally denoted 30, for converting a low frequency clock, such as a parallel data clock, to a high frequency clock, such as that required for serial data transmission. (As summarized above, pursuant to the present invention data serialization is also preferably performed simultaneous with clock frequency multiplication. For Q parallel data bits to be serialized, the parallel clock frequency must be multiplied Q times to produce an appropriate high frequency data clock.)
[0012] In the embodiment shown, the low frequency parallel data clock 32 is fed to a delay line 34 which generates, through a plurality of circuit delays "D", a family of delay clocks f(0), f(1), f(2)..., f(Q-2), f(Q-1) of different phase. The delay clocks, which are each output at one of Q respective taps in line 34, are of the same frequency as low frequency clock 32 but different phase, except for f(0). The total delay T through delay line 34, including a Qth delay D shown in phantom within line 34, equals the low frequency clock period, and the delay D between adjacent delay line taps is defined as:
wherein: Q = low frequency multiplication factor.
[0013] Calibration techniques are known in the art for ensuring that the total delay of line 34 equals the low frequency clock period. When calibrated, f(Q) is in phase with f(0) and one clock period removed therefrom.
[0014] Coupled to each delay line tap is an edge detector 36 configured to detect one of the respective rising and falling delay clock edges. One embodiment of a rising edge detector is depicted in Figure 3. A delay clock f(m), where m = 0, 1, 2..., Q-2, Q-1, is fed simultaneously to one input, herein referred to as the A input, of an "A not B" circuit 38 and simultaneously to the input of a delay Y.
[0015] The output of delay Y is fed to the other input, herein referred to as the B input, of the A not B circuit. "A not B" logic has the following truth table:
| A | B | AnB |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
[0016] Essentially, "A not B" circuit 38, herein after A not B, inverts the B input and then gates the resultant signal in an AND gate with the A input. In Figure 3, the output is a pulse which occurs on the positive clock transition edge. A negative clock transition edge detector is obtained by transposing the connections to the A and B inputs of circuit 38, with the understanding that the B input is to be inverted prior to gating with the A input. The particular circuit requirements will dictate whether edge detector 36 is to be implemented as a rising or falling edge detector. Obviously, with the detector embodiment of Figure 3 Q edge detectors are needed, one for each delay clock f(m) (where m = 0, 1, 2,..., Q-2, Q-1) in order to frequency multiply the parallel data clock Q times.
[0017] Returning to Figure 2, edge detector 36 outputs a pulse S(0), S(1), S(2)..., S(Q-2), S(Q-1) corresponding to each delay clock sampled. In the embodiment of Figure 3, the length of each pulse is defined by delay time Y. Detector output pulses S(0), S(1), S(2)..., S(Q-2), S(Q-1) are input in parallel to an OR circuit 40 which outputs a pulse should any output of edge detector 36 contain a pulse. The desired high frequency clock is available at the output of OR circuit 40.
[0018] A frequency multiplication timing diagram is depicted in Figure 4. Delay clocks f(0), f(1), f(2)..., f(Q-2), and f(Q-1) (f(Q) being equivalent to f(0) after the first cycle) are obtained from delay line 34 by detector 36. Detector 36 outputs pulses S(0), S(1), S(2)..., S(Q-2) and S(Q-1) in response to the corresponding detected delay clock. The output pulses from detector 36 are input in parallel to OR circuit 40 which outputs the desired high frequency clock. Again the high frequency clock output of OR circuit 40 is phase synchronized with the low frequency clock 32 and is Q times the low frequency. Also, as can be observed from the resultant high frequency clock signal depicted in Figure 4, circuit 30 embodies a return-to-zero type (see below) digital clock frequency multiplication technique. (A nonreturn-to-zero digital clock frequency multiplication approach is described below.)
[0019] In another important aspect of the present invention, the digital frequency multiplication and synchronization technique of Figure 2 is modified to provide data serialization simultaneous with frequency multiplication. Two well known formats for data serialization comprise return-to-zero and nonreturn-to-zero data encoding. Briefly described, return-to-zero (RZ) format requires that the coded signal return to a central or zero level between bit cells subsequent a data transition. The more commonly used format is the nonreturn-to-zero (NRZ) data code wherein no return is made to a central or zero level subsequent a data transition. With this encoding technique, the signal remains at a level one for the entire cell containing a one bit and goes to a zero state when there is a zero bit in the cell. Thus, transitions occur only where successive bit cells are in different states. Variations on the nonreturn-to-zero format are described in the open literature, along with other encoding techniques. The present invention described and claimed herein is intended to encompass simultaneous frequency multiplication and data serialization irrespective of the desired serial data format. By way of example, two circuit implementations, one for RZ encoding and the other for NRZ encoding will be described below. Those skilled in the art will recognize from the information provided herein the circuit modifications necessary to implement the concepts of the present invention in association with other encoding techniques.
[0020] Figure 5 depicts one preferred embodiment of a simultaneous frequency multiplication and RZ data serialization circuit, generally denoted 50. Circuit 50 incorporates several components of frequency multiplication circuit 30 (Figure 2). In particular, the low frequency clock input 32, delay line 34, edge detector 36 and OR circuit 40 are identical to the corresponding components described above in connection with the basic frequency multiplication circuit. As an extension, however, edge detector output pulses S(0), S(1), S(2)..., S(Q-2), S(Q-1) are gated into input AND circuits 52 by respective parallel data bits, Bit(0), Bit(1), Bit(2)..., Bit(Q-2), Bit(Q-1). The outputs of AND gates 52 are fed in parallel to OR circuit 40. In combination, AND circuits 52 and OR circuit 40 function as a multiplexer with the parallel data bits serving as the control inputs of the multiplexer. Multiplexer 40 outputs the converted parallel data bits as a serial return-to-zero data stream.
[0021] Figure 6 depicts a sample timing diagram for the simultaneous frequency multiplication and return-to-zero data serialization of an arbitrary signal (Bit(0) = 1, Bit(1) = 1, ..., Bit(Q-2) = 0, Bit(Q-1) = 1). (With reference to this figure, recognize that a pulse from AND circuit 52 will be output only if a data bit (1) within the parallel data bits, Bit(0), Bit(1), Bit (2),... Bit(Q-2), Bit(Q-1), is gated with a respective detector pulse S(0), S(1), S(2)..., S(Q-2), S(Q-1). A data bit (0) will obviously not be gated through an AND circuit as a pulse, but rather as a level zero.
[0022] Figure 7 depicts a further modification of the frequency multiplication circuit of Figure 2. This circuit, denoted 58, provides simultaneous frequency multiplication and nonreturn-to-zero data serialization. The low frequency clock 32 is initially fed to a delay line 60 which outputs a plurality of delay clocks of different phase f(0), f(1), f(2)..., f(Q-2), f(Q-1). As shown, the edge detector of the prior circuit embodiments is replaced here with Q A not B circuits 62. Delays D in delay line 60 also function as delays between inputs to A not B circuits 62. Circuits 62 and their corresponding delays D between inputs can be considered edge detectors (cf. with Figure 3). When data is serialized on the rising clock edge, the f(m-1) delay clock is applied to the A input (see prior discussion in connection with Figure 3) and the f(m) delay clock is applied to the B input of each A not B circuit 62, wherein m = 1, 2, ..., Q. If data is to be serialized on the falling clock edge, then the f(m-1) delay clock is applied to the B input and the f(m) clock is applied to the A input of A not B circuit 62. By using delays D of delay line 60 as the delay between inputs A and B, the output pulses from A not B circuits 62 are equal in length to the phase difference between the delay clocks. AnB circuit output pulses G(0), G(1), G(2),..., G(Q-2), G(Q-1) are gated in respective two input AND circuits 64 by the parallel data bits, Bit(0), Bit(1), Bit(2)... Bit(Q-2), Bit (Q-1). The resultant output signals from AND gates 64 (which remain level (1) or level (0) for the entire respective bit cell) are input in parallel to OR circuit 40 and output therefrom as a serial nonreturn-to-zero data stream.
[0023] A timing diagram for nonreturn-to-zero data serialization is shown in Figure 8 (again, by way of example, Bit(0) = 1, Bit (1) = 1, ... Bit(Q-2) = 0, Bit(Q-1) = 1). If desired, nonreturn-to-zero data serialization and return-to-zero data serialization can be easily intermixed in the same data stream simply by selecting the appropriate circuit scheme (Figure 5 or Figure 7) for different parallel data bits. Also, those skilled in the art will recognize that circuit 50 (Figure 5) or circuit 58 (Figure 7) could be readily modified to accommodate other combinations of encoding techniques. In all circuit embodiments, however, means for generating synchronous clocks of multiple phase are combined with appropriate logic circuitry to simultaneously frequency multiply and data serialize the Q parallel data bits.
[0024] Lastly, those skilled in the art will recognize that the nonreturn-to-zero circuitry of Figure 7 can also be modified for clock frequency multiplication. In particular, by eliminating AND circuits 64, connecting the outputs of A not B circuits 62 in parallel to the inputs of OR circuit 40, and inputting a 101010... low frequency clock signal, a symmetrical, multiplied clock frequency output is obtained.
[0025] It will be observed from the above discussion that simultaneous digital clock frequency multiplication and data serialization is accomplished by the present invention. Further, the digital techniques described herein allow clock frequency multiplication with less jitter than conventional approaches since the circuits are less susceptible to noise. In addition, the data serialization circuits presented do not require latches and are therefore simpler to implement than existing approaches, and can serialize data at a higher rate with less power consumption than existing techniques, i.e., assuming the same technology and circuit speed.
to operate a clock frequency multiplication and data serialization circuit for converting said Q parallel data bits, said circuit comprising:
clock phase generating means (34) coupled to receive the clock signal associated with said Q parallel data bits, said generating means outputting in response thereto Q synchronous clocks each of different phase per clock period; and
logic circuitry (36, 40) coupled to receive said Q synchronous clocks and the Q parallel data bits, said logic circuitry using each of said synchronous clocks to gate a respective one of said Q parallel data bits such that the Q parallel data bits are sequentially output therefrom as a serial data stream having a frequency which is multiple of said first frequency;
the method being characterized by the steps of :
providing a delay line (34, 60) having Q taps, each of said taps outputting one of said Q synchronous clocks of different phase, wherein said Q different clocks having the first frequency and period but are differently delayed in respect to clock pulses of the first frequency,
providing an edge detector (36) for generating Q pulses on an edge of each of the Q different clocks, and
multiplexing each of the parallel data bits by the pulses (S(0)-S(Q-1)) generated by the edge detector.
transforming the falling or rising edges of said Q different clocks into signals with pulses of determined length (Y) and
multiplexing with these signals.
to operate a clock frequency multiplication and data serialization circuit for converting said Q parallel data bits, said circuit comprising:
clock phase generating means (34) coupled to receive the clock signal associated with said Q parallel data bits, said generating means outputting in response thereto Q synchronous clocks each of different phase per clock period; and
logic circuitry (36, 40) coupled to receive said Q synchronous clocks and the Q parallel data bits, said logic circuitry using each of said synchronous clocks to gate a respective one of said Q parallel data bits such that the Q parallel data bits are sequentially output therefrom as a serial data stream having a frequency which is multiple of said first frequency;
characterized by
a delay line (34, 60)), with an input for the clock signals of first frequency and period to generate Q clock signals at outputs ( f(n)) f(n)) of said delay line (34), that are differently delayed in respect to the clock signal of the first frequency,
an edge detector (36) for transforming said edges of the clock signals at the outputs (f(n)) of said delay line (34) at outputs (S(n)) of said edge detectors (36) into signal pulses with a period less or equal to said second period,
a multiplexer circuit having Q inputs (BIT(n)) to receive said Q parallel data bits and a single output (RZ serial data, NRZ serial data), to provide it with a pulse according to the value of the nth bit of the Q parallel data bits, when an edge detected by said edge detector (36) of one of said Q clock signals at the nth of said outputs (f(n)) of said delay line (34) occurs.
that the multiplexer circuit comprises:
a plurality of AND-gates (52; 64), each AND-gate (52; 64) being coupled to receive at a first input one of said signal pulses and at a second input a respective one of the parallel data bits,
an OR-gate (40) for coupling the outputs of the AND-gates (52; 64) together for providing said single output (RZ serial data, NRZ serial data).
that the edge detector (36) outputs a signal pulse on the rising edge of a received clock signal, provided at an output of an A not B logic circuit (38; 62) having an A input and a B input, wherein the A input is coupled to said received clock signal and said B input to the output of a delay (Y;D) delaying said received clock signal.
that the edge detector (36) outputs a signal pulse on the falling edge of a received clock signal, provided at an output of an A not B logic circuit (38; 62) having an A input and a B input, wherein the B input is coupled to said received clock signal and said A input to the output of a delay (Y;D) delaying said received clock signal.
zum Betreiben eines Taktfrequenzmultiplikations- und Datenserialisierungsschaltkreises zum Umwandeln der Q parallelen Datenbits, wobei dieser Schaltkreis beinhaltet:
Taktphasengenerierungsmittel (34), die so geschaltet sind, daß sie das den Q parallelen Datenbits zugeordnete Taktsignal aufnehmen, wobei die Generierungsmittel als Reaktion darauf Q synchrone Takte ausgeben, die jeweils je Taktperiode eine unterschiedliche Frequenz aufweisen; und
eine logische Schaltung (36, 40), die so geschaltet ist, daß sie die Q synchronen Takte und die Q parallelen Datenbits aufnimmt, wobei die logische Schaltung jeden der synchronen Takte benutzt, um ein betreffendes der Q parallelen Datenbits über ein Gatter durchzulassen, so daß die Q parallelen Datenbits von dieser sequentiell als serieller Datenstrom ausgegeben werden mit einer Frequenz, die ein Vielfaches der ersten Frequenz ist;
wobei das Verfahren durch die folgenden Schritte gekennzeichnet ist:
Vorsehen einer Verzögerungsleitung (34, 60) mit Q Abgriffen, so daß jeder dieser Abgriffe jeweils einen der Q synchronen Takte unterschiedlicher Phase ausgibt, wobei die Q unterschiedlichen Takte eine erste Frequenz und Periode aufweisen, jedoch in Bezug auf die Taktimpulse der ersten Frequenz unterschiedlich verzögert werden,
Vorsehen eines Flankendetektors (36) zum Generieren von Q Impulsen jeweils an einer Flanke jedes dieser Q unterschiedlichen Takte, und
Multiplexen jedes dieser parallelen Datenbits durch die Impulse (S(0) -S(Q-1)), die vom Flankendetektor generiert werden.
Umwandeln der abfallenden bzw. ansteigenden Flanken der Q unterschiedlichen Takte in Signale mit Impulsen vorgegebener Länge (Y), und
Multiplexen mit diesen Signalen.
zum Betreiben eines Taktfrequenzmultiplikations- und Datenserialisierungsschaltkreises zum Umwandeln der Q parallelen Datenbits, wobei dieser Schaltkreis beinhaltet:
Taktphasengenerierungsmittel (34), die so geschaltet sind, daß sie das den Q parallelen Datenbits zugeordnete Taktsignal aufnehmen, wobei die Generierungsmittel als Reaktion darauf Q synchrone Takte ausgeben, die jeweils je Taktperiode eine unterschiedliche Frequenz aufweisen; und
eine logische Schaltung (36, 40), die so geschaltet ist, daß sie die Q synchronen Takte und die Q parallelen Datenbits aufnimmt, wobei die logische Schaltung jeden der synchronen Takte benutzt, um ein betreffendes der Q parallelen Datenbits durch ein Gatter durchzulassen, so daß die Q parallelen Datenbits sequentiell von dieser als serieller Datenstrom mit einer Frequenz ausgegeben werden, die ein Vielfaches der ersten Frequenz ist;
gekennzeichnet durch
eine Verzögerungsleitung (34, 60) mit einem Eingang für die Taktsignale der ersten Frequenz und Periode, um an den Ausgängen (f(n)) der Verzögerungsleitung (34) Q Taktsignale zu generieren, die gegenüber dem Taktsignal der ersten Frequenz unterschiedlich verzögert werden,
einen Flankendetektor (36) zum Umwandeln der an den Ausgängen (f(n)) der Verzögerungsleitung (34) stehenden Flanken des Taktsignals an den Ausgängen (S(n)) des Flankendetektors (36) in Signalimpulse mit einer Periode, die kleiner oder gleich der der zweiten Periode ist,
eine Multiplexerschaltung mit Q Eingängen (BIT(n)) zur Aufnahme der Q parallelen Datenbits, und mit einem einzigen Ausgang (RZ serielle Daten, NRZ serielle Daten), um ihm einen Impuls gemäß dem Wert des n-ten Bits der Q parallelen Datenbits zuzuführen, wenn eine vom Flankendetektor (36) erfaßte Flanke eines der Q Taktsignale am n-ten der Ausgänge (f(n)) der Verzögerungsleitung (34) auftritt.
die Multiplexerschaltung beinhaltet:
eine Vielzahl von UND-Gattern (52; 64) wobei jedes UND-Gatter (52; 64) so geschaltet ist, daß es an einem ersten Eingang einen der Signalimpulse, und an einem zweiten Eingang ein entsprechendes der parallelen Datenbits aufnimmt,
ein ODER-Gatter (40) zum Zusammenkoppeln der Ausgänge der UND-Gatter (52; 64), um den einzigen Ausgang (RZ serielle Daten; NRZ serielle Daten) vorzusehen.
daß der Flankendetektor (36) bei einer ansteigenden Flanke eines eingehenden Impulssignals, die am Ausgang eines A NICHT B logischen Schaltkreises (38; 62) mit einem A-Eingang und einem B-Eingang steht, einen Signalimpuls ausgibt, wobei der A-Eingang an das eingehende Taktsignal gekoppelt ist und der B-Eingang am Ausgang einer Verzögerung (Y; D) liegt, die das eingehende Taktsignal verzögert.
daß der Flankendetektor (36) bei einer abfallenden Flanke eines eingehenden Impulssignals, die am Ausgang eines A NICHT B logischen Schaltkreises (38; 62) mit einem A-Eingang und einem B-Eingang steht, einen Signalimpuls ausgibt, wobei der B-Eingang an das eingehende Taktsignal gekoppelt ist und der A-Eingang am Ausgang einer Verzögerung (Y; D) liegt, die das eingegangene Taktsignal verzögert.
un moyen générateur de phase d'horloge (34) couplé pour recevoir le signal d'horloge associé auxdits Q bits de données parallèles, ledit moyen générateur produisant en réponse à celui-ci Q horloges synchrones ayant chacune une période de phase par horloge différente; et
des circuits logiques (36, 40) couplés pour recevoir lesdites Q horloges synchrones et les Q bits de données parallèles, lesdits circuits logiques utilisant chacune desdites horloges synchrones afin d'autoriser le passage d'un bit respectif desdits Q bits de données parallèles pour que les Q bits de données parallèles en sortent en séquentiel sous la forme d'un flot de données en série ayant une fréquence qui est un multiple de ladite première fréquence;
le procédé étant caractérisé par les étapes de:
fournir une ligne à retard (34, 60) ayant Q prises, chacune desdites prises produisant une desdites Q horloges synchrones de phase différente, dans laquelle lesdites Q horloges différentes ont la première fréquence et période mais sont retardées différemment par rapport aux impulsions d'horloge de la première fréquence,
fournir un détecteur de front (36) pour engendrer Q impulsions sur un front de chacune des Q horloges différentes, et
multiplexer chacun des bits de données parallèles par les impulsions (S(0) - S(Q-1) engendrées par le détecteur de front.
transformer les fronts descendants et montants desdites Q horloges différentes, en signaux ayant des impulsions de longueur déterminée (Y), et
multiplexer avec ces signaux.
un moyen générateur de phase d'horloge (34) couplé pour recevoir le signal d'horloge associé auxdits Q bits de données parallèles, ledit moyen générateur produisant en réponse à celui-ci Q horloges synchrones ayant chacune une période de phase par horloge différente; et
des circuits logiques (36, 40) couplés pour recevoir lesdites Q horloges synchrones et les Q bits de données parallèles, lesdits circuits logiques utilisant chacune desdites horloges synchrones afin d'autoriser le passage d'un bit respectif desdits Q bits de données parallèles pour que les Q bits de données parallèles en sortent en séquentiel sous la forme d'un flot de données en série ayant une fréquence qui est un multiple de ladite première fréquence;
caractérisé par
une ligne à retard (34, 60), ayant une entrée pour les signaux d'horloge de première fréquence et période afin d'engendrer aux sorties (f(n)) de ladite ligne à retard (34) Q signaux d'horloge qui soient retardés différemment par rapport au signal d'horloge de la première fréquence,
un détecteur de front (36) pour transformer lesdits fronts des signaux d'horloge aux sorties (f(n)) de ladite ligne à retard (34) aux sorties (S(n)) dudit détecteur de front (36) en des impulsions de signal ayant une période inférieure ou égale à ladite deuxième période,
un circuit multiplexeur ayant Q entrées (Bit(n)) pour recevoir lesdits Q bits de données parallèles et une seule sortie (données en série RZ; données en série NRZ), afin qu'elle ait une impulsion conforme à la valeur du nième bit des Q bits de données parallèles, lorsqu'il apparaît un front détecté par ledit détecteur de front d'un desdits Q signaux d'horloge à la nième desdites sorties (f(n)) de ladite ligne à retard (34).
une pluralité de portes ET (52; 64), chaque porte ET (52; 64) étant couplée pour recevoir à une première entrée une desdites impulsions de signal et, à une deuxième entrée, un bit respectif des bits de données parallèles,
une porte OU (40) pour coupler les sorties des portes ET (52; 64) ensemble pour fournir ladite seule sortie (données en série RZ; données en série NRZ).
le détecteur de front (36) produit une impulsion de signal sur le front montant d'un signal d'horloge reçu fourni à une sortie d'un circuit logique A non B (38; 62) ayant une entrée A et une entrée B, dans lequel l'entrée A est couplée audit signal d'horloge reçu et ladite entrée B, à la sortie d'un retard (Y; D) retardant ledit signal d'horloge reçu.
le détecteur de front (36) produit une impulsion de signal sur le front descendant d'un signal d'horloge reçu fourni à une sortie d'un circuit logique A non B (38; 62) ayant une entrée A et une entrée B, dans lequel l'entrée B est couplée audit signal d'horloge reçu et ladite entrée A, à la sortie d'un retard (Y; D) retardant ledit signal d'horloge reçu.
ledit retard est obtenu par une unité à retard (D) de la ligne à retard (34).