(19)
(11) EP 0 481 454 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
21.10.1992 Bulletin 1992/43

(43) Date of publication A2:
22.04.1992 Bulletin 1992/17

(21) Application number: 91117653.5

(22) Date of filing: 16.10.1991
(51) International Patent Classification (IPC)5: H01L 29/10, H01L 29/784
(84) Designated Contracting States:
DE FR GB

(30) Priority: 17.10.1990 JP 280202/90

(71) Applicant: KABUSHIKI KAISHA TOSHIBA
Kawasaki-shi, Kanagawa-ken 210 (JP)

(72) Inventor:
  • Shirai, Koji, c/o Intellectual Property Division
    Minato-ku, Tokyo 105 (JP)

(74) Representative: Lehn, Werner, Dipl.-Ing. et al
Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20
81904 München
81904 München (DE)


(56) References cited: : 
   
       


    (54) Lateral MOS FET and manufacturing method thereof


    (57) In a lateral MOS FET, a back gate region a part of whose surface is a channel region is formed to surround the drain region, while being in contact with a part of the periphery of the drain region. With this configuration, if a high voltage electrostatic surge invades the drain electrode, a surge current will disperse from the drain region toward the surrounding back gate region. As a result, a rise in the electric potential at the drain region is suppressed smaller. Thus the electric potential hardly exceed the dielectric strength of the gate insulating film, thereby suppressing a breakdown of the gate insulating film and an electrostatic breakdown of the device.









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