Video system controller with a row address override circuit

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(11)

EP 0 481 534 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	26.08.1992 Bulletin 1992/35

(43)	Date of publication A2:
	22.04.1992 Bulletin 1992/17

(21)	Application number: 91121915.2

(22)	Date of filing: 23.07.1985

(51)	International Patent Classification (IPC)⁵: G09G 1/16

(84)	Designated Contracting States:
	DE FR GB

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Priority:

23.07.1984 US 633367
23.07.1984 US 633383
23.07.1984 US 633384
23.07.1984 US 633385
23.07.1984 US 633386
23.07.1984 US 633387
23.07.1984 US 633388
23.07.1984 US 633389

(62)	Application number of the earlier application in accordance with Art. 76 EPC:
	85305225.6 / 0182454

(71)	Applicant: TEXAS INSTRUMENTS INCORPORATED
	Dallas Texas 75265 (US)

(72)	Inventors:
	Bond, Jeffrey C. Sugar Land, TX 77478 (US) Guttag, Karl M. Houston, TX 77099 (US) Thaden, Ribert C. Houston, TX 77036 (US) Pinkham, Raymond Missouri City, TX 77489 (US) Novak, Mark Colorado Springs, CO 80910 (US) Watts, Mark W. Hockley, TX 77447 (US) Vanaken, Jerry Sugar Land, TX 77478 (US) Moravec, John V. Willow Springs, IL. 60480 (US) Albachten, Rudy J., III Centerville, OH 45459 (US)

(74)	Representative: Blanco White, Henry Nicholas et al
	ABEL & IMRAY Northumberland House 303-306 High Holborn London WC1V 7LH London WC1V 7LH (GB)

(56)

References cited: :


	Remarks:
	This application was filed on 20 - 12 - 1991 as a divisional application to the application mentioned under INID code 60.

(54)	Video system controller with a row address override circuit

(57) The present invention is a video system which includes a data processor (1), such as a mircoprocessor, for processing data, a video memory (5) for storing data from the data processor corresponding to an image to be displayed, a display (11), such as a raster scan cathode ray tube, for displaying the image data stored in the video memory means, and a video system controller (3) connected to the video memory (5) for controlling the transfer of data from the video memory (5) to the display (11) and between the data processor (1) and the video memory (5). The video memory (5) is preferrably a multiport dynamic randon access memory including an addressable memory array. The video system controller (3) performs a number of functions including refresh of the dynamic random access memory, multiplexing of the various access requests of the video memory and control of the blanking interval of the display. This is accomplished by having a first portion which operates synchronously with the video memory (5) and a second portion which operates synchronously with the data processor (1). The transfer operations in the video system controller are preferrably controlled through the use of a programmable state machine which manipulates inputs in a logic array.

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