(57) A video memory system is disclosed including a video memory 38, an intermediate buffer
34, a video display control unit (VDUC) 42, and a video processing means 39. The intermediate
buffer 34 is disposed between an external CPU 30 and the video memory 38 to intercept
the address 31, data 32, and read/write signals 33 from the CPU. For read operations,
signals to the video memory 38, and the data read therefrom travel through the buffer
34 to arrive at the CPU 30. For write operations, the intermediate buffer 34 stores
the address and data signals from the CPU 30. The data is later written into the video
memory 38 in response to a time slot reference signal 52.
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