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(11) | EP 0 484 946 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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| (54) |
Decoder for 5B6B code Dekodierer für 5B6B-Kode Decodeur pour code 5B6B |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The present invention relates to a 5B6B coding rule inverse conversion circuit for digital transmission and, in more detail, to improvement of circuit for detecting the mark rate or ratio of 6B code converted by the 5B6B coding rule conversion method.
2. Description of the Prior Art
[0002] In general, a self-timing system for extracting the timing wave from the receiving pulse train itself is widely used in a regenerative repeater to be used in digital transmission. In this timing extraction system, the timing information is sometimes lost on the transmission line, in case the input code series is formed by continuation of zero code such as "000....".
[0003] Therefore, in the digital transmission, the 5B6B coding rule conversion is executed to suppress continuation of zero code in order to avoid such disappearance of the timing information. Here, the 5B6B coding rule conversion means that a digital signal train is divided into groups, each consisting of five bits, and this 5-bit signal is converted into the 5B6B code signal of six bits in accordance with the 5B6B coding rule conversion pattern shown in Fig. 1.
[0004] At the time of reception, the received digital signal train is divided into groups, each consisting of six bits and the original 5-bit signal can be obtained by inverse conversion of the 5B6B coding rule.
[0006] As shown in this figure, the conventional 5B6B coding rule inverse conversion circuit detects a mark rate of the 6-bit signal to be converted inversely and thereafterthe 5B6B coding rule inverse conversion is executed reponsive to such detection of mark rate or ratio. Here, a mark rate means the rate of "ON" bit, namely a bit of logic value "1" in the six bits. In the figure, it is indicated as fractions such as 1/6, 2/6. Namely, the conventional 5B6B coding rule inverse conversion circuit is formed by two mark rate detecting circuits 111, 112, one code inverse conversion circuit 113 and two select circuts 114, 115. The first mark rate detecting circuiti 111 detects the mark rates not listed in the conversion pattern of Fig. 1, namely the mark rate 0/6, 1/6, 2/6, 4/6, 5/6 or 6/6 (where, those not listed in the conversion pattern of Fig. 1 for the mark rates 2/6, 4/6) and outputs the signal S88 when such mark rate is detected. The second mark rate detecting circuit 112 detects the mark rates listed in the conversion pattern of Fig. 1, that is, the mark rate 2/6, 3/6 or 4/6 and then outputs the signal S86 when the mark rate is 2/6 or 4/6 and also outputs the signal S87 when the mark rate is 3/6. The code inverse conversion circuit 113 converts inversely the signal S81 of the six bits, D1∼D6 by the 5B6B coding rule inverse conversion method when the signal S86 is outputted from the second mark rate detecting circuit 112 and then outputs such converted signal as the signal S82 of the five bits. The first select circuit 114 usually outputs the signal S82 as the signal S83 and outputs the signal S85 (the 5-bit signal from D1 to D5) as the signal S83 when the signal S87 is outputted from the second mark rate detecting circuit 112. The second select circuit 115 usually outputs the signal S83 as the signal S84 and outputs the 5-bit digital signal "10101" as the signal S84 when the signal S88 is outputted from the first mark rate detecting circuit 111.
[0007] As explained above, in the conventional 5B6B coding rule inverse conversion circuit, the mark rate of the 6-bit 5B6B code signal is detected. When the mark rate is 2/6, 3/6 or 4/6, the 5B6B coding rule inverse conversion is executed in accordance with the conversion pattern of Fig. 1. When the mark rate is 0/6, 1/6, 2/6, 4/6 or 6/6, the 6-bit 5B6B code signal is converted to the 5-bit signal "10101". Those not listed in the conversion pattern of Fig. 1 correspond to the mark rates 2/6 and 4/6.
[0008] However, such conventional 5B6B coding rule inverse conversion circuit provides a disadvantage that the scale of circuit becomes large and many redundant circuits are included because the mark rate is detected for all patterns of 6-bit signal (64 patterns) for detection of each mark rate by first mark rate detecting circuit 111 and the second mark rate detecting circuit 112.
[0009] From IBM Journal of Research and Development, vol. 27, no. 5, September 1983, New York, pages 440-451, a 8B/10B code with improved error detection is known, wherein the coder is partitioned into 5B/6B and 3B/4B subordinate coders.
SUMMARY OF THE INVENTION
[0010] It is an object of the present invention to provide a 5B6B coding rule inverse conversion circuit which has simplified the circuit structure by reducing a number of patterns for detection of mark rate.
[0011] This object is achieved by a 5B6B coding rule inverse conversion circuit according to claims 1,2 and 6.
[0012] Briefly, the 5B6B coding rule inverse conversion circuit of the present invention comprises a composition including a first decoder for generating the signal of eight patterns from the upper three bits in the six bits signal which has been converted by the 5B6B coding rule conversion method, a second decoder for generating a signal of eight patterns from the lower three bits in the six bits, a mark rate detecting circuit for detecting a mark rate of six bits from the signal of eight patterns from the first and second decoders, a code inverse conversion circuit for converting the six bits into the 5-bit signal by the 5B6B coding rule inverse conversion responsive to the mark rate detected by the mark rate detecting circuit and a select circuit for selecting and outputting any one signal among the 5-bit signal converted inversely by the code inverse converting circuit, signal of upper five bits in the six bits and error signal, responsive to the mark rate detected by the mark rate detecting circuit.
[0013] Other objects and features of the present invention will be further understood from the description of the preferred embodiment with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014]
Fig. 1 is a diagram for explaining conventional conversion pattern of the 5B6B coding rule;
Fig. 2 is a diagram indicating the conventional 5B6B coding rule inserve conversion circuit;
Fig.3 is a block diagram for explaining a first embodiment of the 5B6B coding rule inverse conversion circuit of the present invention;
Fig. 4 is a diagram for indicating a mark rate in each bit pattern by the first embodiment;
Fig. 5 is a circuit diagram indicating a practical example of a first and second 3:8 decoders of Fig. 3;
Fig. 6 and Fig. 7 are circuit diagrams indicating a practical example of the mark rate detecting circuit of Fig. 3;
Fig. 8 is a circuit diagram indicating a practical example of a code inverse covnersion circuit of Fig. 3;
Fig. 9 is a circuit diagram indicating a practical example of a select circuit of Fig. 3;
Fig. 10 is a block diagram for explaining a second embodiment of the present invention;
Fig. 11 is a circuit diagram indicating a practical example of a first mark rate detecting circuit of Fig. 10;
Fig. 12 is a diagram indicating relationship between logical values of the first mark rate detecting circuit and mark rate of three bits;
Fig. 13 is a diagram indicating relationship between result of combination of mark rate of three bits and mark rate of six bits shown in Fig. 12;
Fig. 14 is a diagram indicating a practical circuit composition of the second embodiment;
Fig. 15 is a block diagram for explaining a third embodiment of the present invention;
Fig. 16 is a circuit diagram indicating a practical example of a half-adder shown in Fig. 15;
Fig. 17 is a diagram indicating relationship between logical values of the half-adder and mark rate of two bits;
Fig. 18 is a diagram indicating logical values of input and output of decoders shown in Fig. 15;
Fig. 19 is a circuit diagram indicating a practical example of the 6-bit mark rate deciding circuit of Fig. 15; and
Fig. 20 is a daigram for explaining operation of the 6-bit mark rate deciding circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0015] Three embodiments of the present invention will be explained with reference to the accompanying drawings.
[0016] Fig. 3 is a block diagram schematically indicating a 5B6B coding rule inverse conversion circuit as the first embodiment. In this figure, 1a and 1b denote a first and a second 3-line to 8-line decoder/demultiplexer (hereinafter abbreviated as 3:8 decoder); 2, a mark rate detecting circuit; 3, a code inverse conversion circuit; 4, a select circuit.
[0017] The first 3:8 decoder 1a generates a converted signal S5 of eight patterns from the upper three bits D1∼D3 in the signal S1 of six bits D1∼D6 converted by the 5B6B coding rule conversion method. The second 3:8 decoder 1b generates a converted signal S6 of eight patterns from the lower three bits D4∼D6 in the signal S1 of six bits.
[0018] The mark rate detecting circuit 2 outputs, when the mark rate, namely 2/6 or 4/6, listed in the 5B6B coding rule conversion pattern of Fig. 1 is detected, the signal S7 and also outputs, when the mark rate, namely, 0/6, 1/6, 2/6, 4/6, 5/6 or 6/6, not listed in the conversion pattern of Fig. 1 is detected, the signal S8. The mark rates 2/6, 4/6 correspond to those not listed in the conversion pattern of Fig. 1.
[0019] The code inverse conversion circuit 3 inversely converts, when the mark rate detecting circuit 2 outputs the signal S7, the input signal S1 by the 5B6B coding rule inverse conversion method based on the conversion pattern of Fig. 1 and outputs the signal as the 5-bit signal S2.
[0020] The select circuit 4 selects and outputs three kinds of signals, responsive to output content of the mark rate detecting circuit 2. Namely, when the signal S7. is ouputted from the mark rate detecting circuit 2, the select circuit 4 outputs in direct the output signal S2 of the code inverse conversion circuit 3 as the signal S3. When the signal S8 is outputted from the mark rate detecting circuit 2, the select circuit 4 outputs the preset 5-bit signal "10101" as the signal S3. When both the signals S7 and S8 are not outputted from the mark rate detecting circuit 2, the mark rate is considered as 3/6, the select circuit 4 outputs the signal S4 (5-bit signal D1∼D5) as the signal S3.
[0021] As explained above, in this embodiment, the 6-bit 5B6B code signal S1 is divided into groups of three bits and the first and second 3:8 decoders 1a, 1b generate the converted signals S5, S6 of 16 patterns (eight patterns x 2). The mark rate detecting circuit 2 detects all patterns (44 patterns) of the mark rate other than 3/6 and classifies such patterns into the signals, not listed in the conversion pattern shown in Fig. 1, namely the error signal S8 and the signal S7 listed in the conversion pattern of Fig. 1, and the select circuit 4 selects the signal S2 when the signal S7 is detected, or the signal "10101" when the signal S8 is detected, or the signal S4 when both signals S7 and S8 are not detected, to output the 5-bit signal S3.
[0022] Thereby, the mark rate detecting circuit 2 is not required to detect the mark rate 3/6. Moreover, use of the first and second 3:8 decoders 1a, 1b realizes combination of numerals in detection of mark rate as shown in ① ∼ ⑤ of Fig. 4.
[0023] Since the mark rate detecting circuit 2 detects the mark rate with the 3-bit signals of D1∼D3 and D4∼D6, patterns are overlapped like the patterns (A)∼(L) of each bit patern shown in Fig. 4. It indicates that when the signal of three bits D1∼D3 is "000", if the signal of three bits D4∼D6 is any one of the (A) pattern ("001", "101", "100"), the mark rate becomes 1/6, and when the signal of three bits D1∼D3 is any one of the (H) pattern ("001", "010"), if the signal of three bits D4∼D6 is any one of the (A) pattern, the mark rate becomes 2/6.
[0024] As explained above, the mark rate detecting circuit 2 has a circuit composition suitable for simplification so that when the (A) pattern is detected, as indicated by ① ∼ ⑤ of Fig. 4, if the signal of three bits D1 D3 is "000", the mark rate is 1/6 and if the (H) pattern is detected, the mark rate is 2/6.
[0025] Since the mark rates 2/6 and 4/6 show the same pattern if "1" and "0" are inverted as shown in the conversion pattern of Fig. 1, the code inverse conversion circuit 3 inputs in direct the 6-bit signal S1 when the mark rate 2/6 is detected and inputs the signal S1 after polarity inversion when the mark rate is 4/6. For inverse conversion to 5-bit from 6-bit, the inverse conversion is executed by detecting only the pattern with the mark rate 2/6. In this case, since the number of "1" is two when the mark rate is 2/6, the inverse conversion is executed easily in the circuit depending on the position of "1".
[0026] In the select circuit 4, five 3-line to 1-line type select circuits (hereinafter abbreviated as 3:1 select circuit) are used in place of 10 conventional 2-line to 8-line type select circuits. This select circuit 4 is necessary for all five bits of the output signal S3 and two stages of select circuits have been employed. Therefore the circuit scale has been large. But, use of the 3:1 select circuit has realized scale-down of circuit structure and reduction of redundant circuits.
[0027] The paractical composition of each circuit will be explained with reference to Fig. 3∼ Fig. 7.
[0028] Fig. 5 is a circuit diagram of the first and second 3:8 decoders 1a, 1b. As shown in this figure, the 5B6B code signals S11∼S18 of six bits D1∼D6 are inputted in unit of thre bits and are then converted into the signals S50∼S57 and S60∼S67 of eight patterns.
[0029] Fig. 6 indicates a circuit diagram of the part 2A for detecting the mark rates 0/6, 1/6, 2/6, 4/6, 5/6, 6/6 of the mark rate detecting circuit 2.
[0030] In this figure, the mark rates 0/6, 1/6 indicated by ① of Fig. 4 are detected by respectively inputting the output signal of the AND circuit 25 for detecting (A) pattern of Fig. 4 and the output signal S50 of decoder 1a, and also inputting the output signal of AND circuit 21 for detecting (C) pattern of Fig. 4 and the output signal S60 of decoder 1b to the NAND circuit 22.
[0031] The mark rates 5/6, 6/6 indicated by ② of Fig. 4 are detected by respectively inputting the output signal of AND circuit 26 for detecting (B) pattern of Fig. 4 and the output signal S57 of decoder 1a, and also inputting the output signal of AND circuit 23 for detecting (D) pattern of Fig. 4 and the output signal S67 of decoder 1b to the NAND circuit 24.
[0032] The mark rates 2/6, 4/6 indicated by ⑤ of Fig. 4 are detected by respectively inputting the signals S50, S63, signals S51 S67, signals S53, S66, signals S54, S61, signals S56, S60 ans signals S57, S64 to the NOR circuits 27∼2C.
[0033] The mark rates 0/6, 1/6, 2/6, 4/6, 5/6, 6/6 not listed in the conversion pattern of Fig. 1 are detected as the error by the NOR circuit 2D, NOR circuit 2E and NAND circuit 2F and the error detection signal S8 is outputted.
[0034] Fig. 7 is an electrical circuit of the part 2B for detecting the mark rates 2/6 and 4/6 of the mark rate detecting circuit 2.
[0035] In this circuit, the mark rate indicated by ③ of Fig. 4 is detected as explained hereunder. Namely, the patterns (E)∼(H) of Fig. 4 are detected by four AND circuits 2R∼2U. In practical, the pattern (E) is detected by inputting the signals S65 and S66 to the AND circuit 2R, the pattern (F) is detected by inputting the signals S62 and S64 to the AND circuit 2T, the pattern (G) is detected by inputting the signals S53 and S55 to the AND circuit 2U and the pattern (H) is detected by inputting the signals S51 and S52 to the AND circuit 2S.
[0036] Next, after each pattern is detected by inputting these pattern signals of (E)∼(H), signal S50, signal ①, signal S54, signal S60 of Fig. 6 to the four NOR circuits 2G∼2J, thee signals are then inputted to the NOR circuit 20 to output the detected signal S71 with mark rate 2/6.
[0037] Moreover, the mark rate 4/6 indicated by ④ of Fig. 4 is detected as explained hereunder. That is, four AND circuits 2V∼2Y detect the patterns (I)∼(L) of Fig. 4. In practical, the (I) pattern is detected by inputting the signals S61 and S62 to the AND circuit 2V, the (J) patern by inputting the signals S63 and S65 to the AND circuit 2W, the (K) pattern by inputting the signals S52 and S54 to the AND circuit 2X and the (L) pattern by inputting the signals S55 and S56 to the AND circuit 2Y.
[0038] Next, after each pattern is detected by inputting these (I)∼(L) patterns, signal S57, signal ②, signals S53, S67 of Fig. 6 to four NOR circuits 2K∼2N, the mark rate 4/6 is detected by inputting these signals to the NOR circuit 2P. The detected sisgnal S72 of the mark rates 2/6 and 4/6 is also outputted by inputting the detected signal S71 of mark rate 2/7 and the detected signal of mark rate 4/6 to the NAND circuit 2Q.
[0039] Fig. 8 is a circuit diagram indicating a practical example of a code inverse conversion circuit 3.
[0040] In this circuit, since the bit patterns of mark rates 2/6 and 4/6 are same as explained above by inverting "1" and "0". Accordingly, if the detected signal S71 of the mark rate 2/6 is "0", the signal of positive logic is outputted from the 5B6B code signals S11∼S16 of six bits by the inverter circuits 3N 3S and select circuits 31 36. Moreover, when the detected signal S71 of the mark rate 2/6 is "1", the mark rate is changed to 2/6 when the select circuits 31∼36 output the negative logic signal. That is, since the patterns having the mark rates other than 2/6 and 4/6 can be neglected without 5B6B coding rule conversion, it is necessary to detect only each bit pattern of the mark rate 2/6.
[0041] Detection of individual bit pattern of mark rate 2/6 is executed responsive to the position of a couple of "1" in the 5B6B code signals S11∼S16 of six bits. This detection is carried out by the NAND circuits 37∼3H and this NAND circuit 37∼3H also output the signals S21∼S25 converted in the NAND circuits 3I∼3M by the detected pattern.
[0042] Only 11 patterns among 12 patterns having the mark rate 2/6 are detected because detection of all patterns is not required since when "000101" is not detected, all NAND circuits 37∼3H output "1" and the NAND circuits 3I∼3M output "0".
[0043] Fig. 9 is a detail circuit diagram of the select circuit 4. As shown in this figure, the select circuits 41∼45 are controlled by a couple of control signals. The one control signal is the detected signal S72 of the mark rates 2/6 and 4/6 explained above and the other control signal is the error detection signal S8 explained above.
[0044] Here, when the one control signal S72 is "1", the signals S21∼S25 converted by the 5B6B coding rule inverse conversion are selected. When the other control singal S8 is "1", the error signal "10101" is selected. When both control signals S8 and S72 are "0", the signals S11∼S15 are selected. Thereby, five select circuits 41∼45 output the signals S31∼S35.
[0045] Next, the second embodiment of the present invention will be explained with reference to Fig. 10 to Fig. 14.
[0046] Fig. 10 is a diagram for explaining the fundamental composition of the second embodiment of the present invention.
[0047] As shown in Fig. 10, the 5B6B coding rule inverse conversion circuit of this embodiment comprises a first mark rate detecting circuit 51 for detecting the mark rate of upper three bits D1∼D3, a second mark rate detecting circuit 52 for detecting mark rate of lower three bits D4∼D6 and a 6-bit mark rate deciding circuit 53 for deciding the mark rate of six bits D1∼D6 from the mark rate detected by the first and second mark rate detecting circuits 51, 52. This embodiment shows only the circuit portion for detecting the mark rate of six bits.
[0048] Namely, in this embodiment, the 5B6B code signal of six bits D1∼D6 is divided into two groups of three bits as in the case of the preceding embodiment. In this case, logical sum (OR), logical product (AND) and exclusive logical sum (EOR) are taken for individual three bits without using the 3:8 decoder in order to detect respective mark rates.
[0049] These logical circuits are shown in Fig. 11 and logical values are shown in Fig. 12. From output of the logical circuits of Fig. 11, the mark rate of three bits can be detected as shown in Fig. 12 as explained hereunder.
[0050] Namely, the mark rate of three bits can be detected under the conditions:
① the mark rate is 0/3 when a value of OR circuit is "0";
② the mark rate is 1/3 when a value of OR circuit is "1", a value of AND circuit is "0" and a value of EOR circuit is "1";
③ the mark rate is 2/3 when a value of OR circuit is "1", a value of AND circuit is "0" and a value of EOR circuit is "0";
④ the mark rate is 3/3 when a value of AND circuit is "1".
[0051] The mark rate of six bits as shown in Fig. 13 can be obtained from combination of the mark rates. For example, the mark rate 0/6 of six bits can be obtained from combination, for example, of the mark rate 0/3 of upper three bits and the mark rate 0/3 of lower three bits. Moreover, the mark rate 3/6 of six bits can be obtained from combination of the mark rate 0/3 of upper three bits and the mark rate 3/3 of lower three bits. In the same manner, the mark rate 6/6 of six bits can be obtained from combination of the mark rate 3/3 of upper three bits and the mark rate 3/3 of lower three bits.
[0052] Fig. 14 shows a practical example of the circuit shown in Fig. 10. In this circuit, the circuits enclosed by broken lines respectively correspond to the circuits shown in Fig. 10. The first mark rate detecting circuit 51 is formed by a NOR circuit 51a, an AND circuit 51b, an EOR circuit 51c, a NOR circuit 51d and a NOR circuit 51e. The second mark rate detecting circuit 52 is formed by a NOR circuit 52a, an AND circuit 52b, an EOR circuit 52c, a NOR circuit 52d and a NOR circuit 52e. These two mark rate detecting circuits 51 and 52 are similar in function to so-called half-adder circuits, except that three inputs are provided to each of circuits 51 and 52 (D1-D3 for circuit 51, and D4-D6 for circuit 52), rather than two inputs which are conventionally known in the case of a half-adder.
[0053] Moreover, a 6-bit mark rate deciding circuit 53 is formed by 12 AND circuits 61∼69, 6A∼6C and four OR circuits 53a, 53b, 53c, 53d.
[0054] As explained above, also in the second embodiment, the 6-bit 5B6B code signal is divided into the upper three bits and lower three bits and the mark rate of the 5B6B code signal is detected from these patterns. Thereby, a number of detected patterns can be reduced in number and the circuit composition can be scaled down more than that of the conventional circuit.
[0055] Next, the third embodiment as a modification of the second embodiment explained above will then be explained. In this third embodiment, the 6-bit 5B6B code signal is divided in unit of two bits. The signals of upper and intermediate and lower two bits are respectively applied to a half-adder to detect the mark rate signal of two bits. Next, the upper bits signal and lower bits signal of the mark rate signals of these two bits are respectively inputted to different 3:8 decoders so that these decoders generate respectively the converted signals of eight patterns. Finally, the converted signals of 16 patterns (eight patterns x 2) are inputted to the 6-bit mark rate deciding circuit to detect the mark rate of six bits.
[0056] Fig. 15 is a block diagram indicating a fundamental structure of a third embodiment. In this figure, 71, 72, 73 denote a first, a second and a third half-adder; 81, 82, a first and a second 3:8 decoders; 91, a 6-bit mark rate deciding circuit.
[0057] The signals of upper two bits D1, D2 among the 5B6B code signals of D1∼D6 are inputted to the first half-adder 71, the signals of intermediate two bits D3, D4 are inputted to the second half-adder 72 and the signals of lower two bits D5, D6 are input to the third half-adder 73, respectively. These three half-adders 71, 72, 73 have the same circuit structure and therefore the circuit of the first half-adder 71 is representatively shown in Fig. 16. As shown in this figure, a half-adder is formed by an exclusive NOR circuit 711 and an OR circuit 712. These circuits make logical sum (OR) of the signals of upper two bits D1, D2 to be applied to a couple of input terminals A, B and detect the mark rate of two bits from combination of logical values outputted from the output terminals XS, XC of both circuits. Fig. 17 is a diagramm indicating the logical values of the input and output of decoders 81 and 82. As can be understood from this figure, for example, when the signals of upper two bits D1, D2 are respectively "0", the 2-bit mark rate 0/2 is detected. When both D1, D2 are "1", the 2-bit mark rate 2/2 is detected. In other cases, the 2-bit mark rate 1/2 is detected. Here, the logical value signal of output terminal XS of half-adder is defined as the upper bit signal of 2-bit mark rate signal and the logical value signal of output terminal XC as the lower bit signal thereof for the convenience of explanation.
[0058] The first 3:8 decoder 81 respectively inputs the upper bit signal among 2-bit mark rate signals outputted from three half-adders 71∼73 and outputs the logical value signal DS1 of eight patterns by demultiplexing the input 3-bit logical value signals. The second 3:8 decoder 82 respectively inputs the lower bit signal among 2-bit mark rate signals and outputs the logical value signal DS2 of eight patterns. Fig. 18 is a diagramm indicating the relationship between logical values of the half-adder circuits and the mark rate of two bits.
[0059] The 6-bit mark rate deciding circuit 91 is formed, as indicated practically in Fig. 19, by 15 inverters 911∼925, 11 AND circuits 931∼941 and seven OR circuits 951∼957 and detects 6-bit mark rates by logical operations of the logical value signals of 32 patterns to be outputted from the first and second 3:8 decoders 81, 82. In practice, the inverters 911∼925 invert polarity of logical value signals outputted from the decoders 81, 82 and the AND circuits 931∼941 and OR circuits 951∼957 result in the logical product and logical sum of the polarity-inverted signals.
[0060] An output of the inverter 911 is detected as 6-bit mark rate 0/6, an output of OR circuit 955 is detected as 6-bit mark rate 1/6, an output of OR circuit 956 is detected as 6-bit mark rate 2/6, an output of OR circuit 957 is detected as 6-bit mark rate 4/6, an output of OR circuit 957 is detected as 6-bit mark rate 4/6, an output of AND circuit 940 is detected as 6-bit mark rate 5/6 and an output of AND circuit 941 is detected as 6-bit mark rate 6/6, respectively. When these six mark rates are not detected completely, the 6-bit mark rate 3/6 is detected.
[0061] Fig. 20 shows relationship between the logical values of decoder and 6-bit mark rates, with the relationship between the 5B6B code signals D1∼D6 and output signals of half-adders. The mark rates 1/6, 2/6, 4/6 and 5/6 are representative examples and other mark rates are also detected.
[0062] According to modification examples, a number of detected patterns can be reduced to about 20 patterns which are about 1/3 of the conventioanl patterns and thereby the circuit structure can be scaled down. Moreover, with simplification of the circuits, cost reduction can be realized through reduction of power consumption.
a first decoder (1a) for generating a signal of eight patterns from the upper three bits in a six bits signal which has been converted by the 5B6B coding rule conversion method;
a second decoder (1b) for generating the signal of eight patterns from the lower three bits in the six bits;
a mark rate detecting circuit (2) for detecting a mark rate of six bits from the signal of eight patterns outputted from the first and second decoders;
a code inverse conversion circuit (3) for executing the inverse conversion of the 5B6B coding rule responsive to the mark rates detected by the mark rate detecting circuit (2) in order to convert the six bits into a signal of five bits; and
a select circuit (4) for selecting and outputting only one signal among the signal of five bits inversely converted by the code inverse conversion circuit (3), the signal of upper five bits among the six bits and an error signal, responsive to the mark rate detected by the mark rate detecting circuit (2).
a first mark rate detecting circuit (51) for detecting a mark rate of upper three bits in a six bits signal which has been converted by the 5B6B coding rule conversion method;
a second mark rate detecting circuit (52) for detecting the mark rate of lower three bits for the six bits; and
a 6-bit mark rate deciding circuit (53) for deciding the mark rate of the six bits, responsive to the mark rate detected by the first mark rate detecting circuit (51) and the second mark rate detecting circuit (52).
a first NOR circuit (51a), an AND circuit (51b), and an EOR circuit (51c) receiving in parallel said upper three bits;
an inverter connected to receive an output of said EOR circuit (51c), and
a second NOR circuit (51d) and a third NOR circuit (51e) receiving the outputs of said first NOR circuit (51a) and said AND circuit (51b), said EOR circuit (51c) supplying an output to said second NOR circuit (51d) and to said inverter, said inverter supplying its output to said third NOR circuit (51e), such that said third NOR circuit (51c) receives a signal corresponding to the inverted output of said EOR circuit (51c).
a first NOR circuit (52a), an AND circuit (52b), and an EOR circuit (52c) receiving in parallel said upper three bits;
an inverter connected to receive an output of said EOR circuit (52c) and
a second NOR circuit (52d) and a third NOR circuit (52e) receiving the outputs of said first NOR circuit (52a) and said AND circuit (52b), said EOR circuit (52c) supplying an output to said second NOR circuit (52d) and to said inverter, said inverter supplying its output to said third NOR circuit (52e), such that said third NOR circuit (52e) receives a signal corresponding to the inverted output of said EOR circuit (52c).
a plurality of AND circuits (61-69; 6A-C) disposed in parallel, said plurality of AND circuits being connected to receive outputs of said second and third NOR circuits (51a,51d) of said first mark rate detecting circuit (51) and said second and third NOR circuits (52a,52d) of said second mark rate detecting circuit (52), and wherein one of said plurality of AND circuits receives the output from said first NOR circuit (51a) of said first mark rate detecting circuit (51), and wherein another one of said plurality of AND circuits receives the output from said first NOR circuit (52a) of said second mark rate detecting circuit (52).
a first half-adder (71) for detecting a mark rate of upper two bits in a six bits signal which has been converted by the 5B6B coding rule conversion method and separately outputting an upper bit and a lower bit of said upper two bits in the six bits signal;
second half-adder (72) for detecting the mark rate of intermediate two bits of the six bits and separately outputting an upper bit and a lower bit of said intermediate two bits in the six bits signal;
a third half-adder (73) for detecting the mark rate of lower two bits for the six bits and separately outputting an upper bit and a lower bit of said lower two bits in the six bits signal;
a first decoder (81) having three input terminals respectively receiving the upper bit separately output from each of said first, second, and third half-adders (71-73), for generating a logical signal of eight patterns from the logical signal of the upper bit of respective 2-bit logical signals detected by each of said first, second, and third half-adders (71-73), indicating the mark rate detected by each of said first, second, and third half-adders (71-73);
a second decoder (82) having three input terminals respectively receiving the lower bit separately output from each of said first, second, and third half-adders (71-73), for generating the logical signal of eight patterns from the logical signal of the lower bit of respective 2-bit logical signals detected by each of said first, second, and third half-adders (71-73), indicating the mark rate, and
a 6-bit mark rate deciding circuit (91) for deciding mark rates of the six bits, responsive to a total of 16 patterns generated by the first and second decoders (81,82).
einen ersten Decodierer (1a), um aus den oberen drei Bits eines sechs Bits umfassenden Signals, welches mithilfe des 5B6B-Codiervorschrift-Umsetzverfahrens umgewandelt worden ist, ein Signal mit acht Mustern zu erzeugen,
einen zweiten Decodierer (1b), um aus den unteren drei Bits der sechs Bits ein Signal mit acht Mustern zu erzeugen,
eine Markierungsrate-Erfassungsschaltung (2), um ausgehend von dem acht Muster umfassenden und von den ersten und zweiten Decodierern ausgegebenen Signal eine Markierungsrate der sechs Bits zu erfassen,
eine Coderückumwandlungsschaltung (3), um abhängig von den durch die Markierungsrate-Erfassungsschaltung (2) erfaßten Markierungsraten die Rückumwandlung der 5B6B-Codiervorschrift durchzuführen, um die sechs Bits in ein Signal mit fünf Bits umzuwandeln, und
eine Auswahlschaltung (4), um abhängig von der durch die Markierungsrate-Erfassungsschaltung (2) erfaßten Markierungsrate aus dem fünf Bits umfassenden und durch die Coderückumwandlungsschaltung (3) zurückumgewandelten Signal, dem die oberen fünf Bits der sechs Bits umfassenden Signal sowie einem Fehlersignal lediglich ein Signal auszuwählen und dieses auszugeben.
eine erste Markierungsrate-Erfassungsschaltung (51) zum Erfassen einer Markierungsrate von den oberen drei Bits eines sechs Bits umfassenden Signals, welches mithilfe des 5B6B-Codiervorschrift-Umwandlungsverfahren umgewandelt worden ist,
eine zweite Markierungsrate-Erfassungsschaltung (52) zum Erfassen der Markierungsrate der unteren drei Bits der sechs Bits, und
eine 6-Bit-Markierungsrate-Bestimmungsschaltung (53) zum Bestimmen der Markierungsrate der sechs Bits abhängig von der durch die erste Markierungsrate-Erfassungsschaltung (51) und der zweiten Markierungsrate-Erfassungsschaltung (52) erfaßten Markierungsrate.
dadurch gekennzeichnet,
daß die erste Markierungsrate-Erfassungsschaltung (51) beinhaltet:
eine erste NOR-Schaltung (51a), eine AND-Schaltung (51b) und eine EOR-Schaltung (51c), die parallel die oberen drei Bits empfangen,
einen Inverter, der derart verschaltet ist, daß er ein Ausgangssignal der EOR-Schaltung (51c) empfängt, und
eine zweite NOR-Schaltung (51d) und eine dritte NOR-Schaltung (51e), die die Ausgangssignale der ersten NOR-Schaltung (51a) und der AND-Schaltung (51b) empfangen, wobei die EOR-Schaltung (51c) ein Ausgangssignal der zweiten NOR-Schaltung (51d) sowie dem Inverter zuführt, und wobei der Inverter sein Ausgangssignal der dritten NOR-Schaltung (51e) derart zuführt, daß die dritte NOR-Schaltung (51e) ein dem invertierten Ausgangssignal der EOR-Schaltung (51c) entsprechendes Signal empfängt.
dadurch gekennzeichnet,
daß die zweite Markierungsrate-Erfassungsschaltung (52) beinhaltet:
eine erste NOR-Schaltung (52a), eine AND-Schaltung (52b) und eine EOR-Schaltung (52c), die die oberen drei Bits parallel empfangen,
einen Inverter, der derart verschaltet ist, daß er ein Ausgangssignal der EOR-Schaltung (52c) empfängt, und
eine zweite NOR-Schaltung (52d) und eine dritte NOR-Schaltung (52e), die die Ausgangssignale der ersten NOR-Schaltung (52a) und der AND-Schaltung (52b) empfangen, wobei die EOR-Schaltung (52c) ein Ausgangssignal der zweiten NOR-Schaltung (52d) sowie dem Inverter zuführt, und wobei der Inverter sein Ausgangssignal der dritten NOR-Schaltung (52e) derart zuführt, daß die dritte NOR-Schaltung (52e) ein dem invertierten Ausgangssignal der EOR-Schaltung (52c) entsprechendes Signal empfängt.
dadurch gekennzeichnet,
daß die 6-Bit-Markierungsrate-Bestimmungsschaltung (53) beinhaltet:
eine Vielzahl von parallel angeordneten AND-Schaltungen (61-69; 6A-C), wobei die Vielzahl von AND-Schaltungen derart verschaltet ist, daß die AND-Schaltungen Ausgangssignale der zweiten und dritten NOR-Schaltungen (51a, 51d) der ersten Markierungsrate-Erfassungsschaltung (51) und der zweiten und dritten NOR-Schaltungen (52a, 52d) der zweiten Markierungsrate-Erfassungsschaltung (52) empfangen, und wobei eine der Vielzahl von AND-Schaltungen das Ausgangssignal von der ersten NOR-Schaltung (51a) der ersten Markierungsrate-Erfassungsschaltung (51) empfängt, und wobei eine andere der Vielzahl von AND-Schaltungen das Ausgangssignal von der ersten NOR-Schaltung (52a) der zweiten Markierungsrate-Erfassungsschaltung (52) empfängt.
einen ersten Halbaddierer (71) zum Erfassen einer Markierungsrate der oberen zwei Bits eines sechs Bits umfassenden Signals, welches mithilfe des 5B6B-Codiervorschrift-Umwandlungsverfahren umgewandelt worden ist, und zum getrennten Ausgeben eines oberen Bits und eines unteren Bits der beiden oberen Bits des sechs Bits umfassenden Signals,
einen zweiten Halbaddierer (72) zum Erfassen der Markierungsrate von mittleren zwei Bits der sechs Bits und zum getrennten Ausgeben eines oberen Bits und eines unteren Bits der mittleren zwei Bits des sechs Bits umfassenden Signals,
einen dritten Halbaddierer (73) zum Erfassen der Markierungsrate der unteren zwei Bits der sechs Bits und zum getrennten Ausgeben eines oberen Bits und eines unteren Bits der unteren beiden Bits des sechs Bits umfassenden Signals,
einen ersten Decodierer (81) mit drei Eingangsanschlüssen, die das getrennt von dem ersten, zweiten bzw. dritten Halbaddierer (71-73) ausgegebene obere Bit empfangen, um ausgehend von dem logischen Signal des oberen Bits von logischen 2-Bit-Signalen, welche von dem ersten, zweiten bzw. dritten Halbaddierer (71-73) erfaßt werden, ein logisches Signal mit acht Mustern zu erzeugen, welches die von dem ersten, zweiten und dritten Halbaddierer (71-73) erfaßten Markierungsrate bezeichnet,
einen zweiten Decodierer (82) mit drei Eingangsanschlüssen, die das von dem ersten, zweiten bzw. dritten Halbaddierer (71-73) getrennt ausgegebene untere Bit empfangen, um ausgehend von dem logischen Signal des unteren Bits von logischen 2-Bit-Signalen, welche von dem ersten, zweiten bzw. dritten Halbaddierer (71-73) erfaßt werden, ein logisches Signal mit acht Mustern zu erzeugen, welches die Markierungsrate bezeichnet, und
eine 6-Bit-Markierungsrate-Bestimmungsschaltung (91) zum Bestimmen der Markierungsraten der sechs Bits abhängig von insgesamt 16 Mustern, die von dem ersten und dem zweiten Decodierer (81, 82) erzeugt werden.
un premier décodeur (1a) destiné à générer un signal selon huit grilles à partir des trois bits supérieurs d'un signal à six bits qui a été converti par le procédé de conversion selon la règle de codage 5B6B,
un second décodeur (1b) destiné à générer le signal selon huit grilles à partir des trois bits inférieurs parmi les six bits,
un circuit de détection de taux de marqueurs (2) destiné à détecter un taux de marqueurs de six bits d'après le signal selon huit grilles, fourni en sortie à partir des premier et second décodeurs,
un circuit de conversion inverse de code (3) destiné à exécuter la conversion inverse selon la règle de codage 5B6B, en réponse aux taux de marqueurs détectés par le circuit de détection de taux de marqueurs (2) de manière à convertir les six bits en un signal de cinq bits, et
un circuit de sélection (4) destiné à sélectionner et à ne fournir en sortie qu'un seul signal parmi le signal de cinq bits converti en inverse par le circuit de conversion inverse de code (3), le signal de cinq bits supérieurs parmi les six bits et un signal d'erreur, en réponse au taux de marqueurs détecté par le circuit de détection de taux de marqueurs (2).
un premier circuit de détection de taux de marqueurs (51) destiné à détecter un taux de marqueurs des trois bits supérieurs dans un signal de six bits qui a été converti par le procédé de conversion selon la règle de codage 5B6B,
un second circuit de détection de taux de marqueurs (52) destiné à détecter le taux de marqueurs des trois bits inférieurs pour les six bits, et
un circuit de définition de taux de marqueurs à 6 bits (53) destiné à définir le taux de marqueurs des six bits, en répondant au taux de marqueurs détecté par le premier circuit de détection de taux de marqueurs (51) et le second circuit de détection de taux de marqueurs (52).
un premier circuit NON OU (51a), un circuit ET (51b), et un circuit OU EXCLUSIF (51c) recevant en parallèle lesdits trois bits supérieurs,
un inverseur relié de façon à recevoir une sortie dudit circuit OU EXCLUSIF (51c), et
un second circuit NON OU (51d) et un troisième circuit NON OU (51e) recevant les sorties dudit premier circuit NON OU (5 la) et dudit circuit ET (51b), ledit circuit OU EXCLUSIF (51c) fournissant une sortie audit second circuit NON OU (51d) et audit inverseur, ledit inverseur fournissant sa sortie audit troisième circuit NON OU (51e) de sorte que ledit troisième circuit NON OU (51e) reçoit un signal correspondant à la sortie inversée dudit circuit OU EXCLUSIF (51c).
un premier circuit NON OU (52a), et un circuit ET (52b), ainsi qu'un circuit OU EXCLUSIF (52c) recevant en parallèle lesdits trois bits supérieurs,
un inverseur relié de façon à recevoir une sortie dudit circuit OU EXCLUSIF (52c), et
un second circuit NON OU (52d) et un troisième circuit NON OU (52e) recevant les sorties dudit premier circuit NON OU (52a) et dudit circuit ET (52b), ledit circuit OU EXCLUSIF (52c) fournissant une sortie audit second circuit NON OU (52d) et audit inverseur, ledit inverseur fournissant sa sortie audit troisième circuit NON OU (52e), de sorte que ledit troisième circuit NON OU (52e) reçoit un signal correspondant à la sortie inversée dudit circuit OU EXCLUSIF (52c).
une pluralité de circuits ET (61 à 69, 6A à C) disposés en parallèle, ladite pluralité de circuits ET étant reliée de façon à recevoir des sorties desdits second et troisième circuits NON OU (51a, 51d) dudit premier circuit de détection de taux de marqueurs (51) et desdits second et troisième circuits NON OU (52a, 52d), dudit second circuit de détection de taux de marqueurs (52), et dans lequel un circuit parmi ladite pluralité des circuits ET reçoit la sortie provenant dudit premier circuit NON OU (51a) dudit premier circuit de détection de taux de marqueurs (51), et dans lequel un autre circuit parmi ladite pluralité des circuits ET reçoit la sortie provenant dudit premier circuit NON OU (52a) dudit second circuit de détection de taux de marqueurs (52).
un premier demi-additionneur (71) destiné à détecter un taux de marqueurs des deux bits supérieurs d'un signal à six bits qui a été converti par le procédé de conversion selon la règle de codage 5B6B et fournissant séparément en sortie un bit supérieur et un bit inférieur desdits deux bits supérieurs du signal à six bits,
un second demi-additionneur (72) destiné à détecter le taux de marqueurs des deux bits intermédiaires parmi les six bits et à fournir séparément en sortie un bit supérieur et un bit inférieur desdits deux bits intermédiaires du signal à six bits,
un troisième demi-additionneur (73) destiné à détecter le taux de marqueurs des deux bits inférieurs pour les six bits, et à fournir séparément en sortie un bit supérieur et un bit inférieur desdits deux bits inférieurs du signal à six bits,
un premier décodeur (81) comportant trois bornes d'entrée, recevant respectivement le bit supérieur sorti séparément depuis chacun desdits premier, second, et troisième demi-additionneurs (71 à 73), afin de générer un signal logique de huit grilles à partir du signal logique du bit supérieur des signaux logiques à 2 bits respectifs détectés par chacun desdits premier, second et troisième demi-additionneurs (71 à 73), indiquant le taux de marqueurs détecté par chacun desdits premier, second, et troisième demi-additionneurs (71 à 73),
un second décodeur (82) comportant trois bornes d'entrée, recevant respectivement le bit inférieur sorti séparément depuis chacun desdits premier, second et troisième demi-additionneurs (71 à 73), afin de générer le signal logique selon huit grilles à partir du signal logique du bit inférieur des signaux logiques à 2 bits respectifs détectés par chacun desdits premier, second et troisième demi-additionneurs (71, 73), indiquant le taux de marqueurs, et
un circuit de définition de taux de marqueurs à 6 bits (91) destiné à définir des taux de marqueurs des six bits, en réponse à un total de 16 grilles générées par les premier et second décodeurs (81, 82).