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(11) | EP 0 492 776 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | A semiconductor memory device with a large storage capacity memory and a fast speed memory |
| (57) A semiconductor memory device containing a cache includes a SRAM (2) as a cache memory,
and a DRAM (1) as a main memory. Collective transfer of data blocks is possible between
the DRAM array (1) and the SRAM array (2) through a bi-directional transfer gate circuit
(3) and through an internal data line (SBL and 16a and 16b). A DRAM row decoder (14)
and a DRAM column decoder (15) are provided in the DRAM array (1). A SRAM zow decoder
(21) and an SRAM column decoder (22) are provided in the SRAM array (2). Addresses
of the SRAM array 2 and DRAM array 1 can be independently applied. The data transfer
gate includes a latch circuit (1811) for latching data from the SRAM (2) as a high
speed memory, an amplifier circuit (1814) and a gate circuit (1815) for amplifying
data from the DRAM (1) as a large capacity memory and for transmitting the same to
the SRAM, and a gate circuit (1813) responsive to a DRAM write enable signal (AWDE)
for transmitting write data to corresponding memory cells of the DRAM. After the data
of the SRAM has been latched by a latch circuit (1811), write data is transmitted
from the gate circuit (1813) to the DRAM, and the write data is transmitted to the
SRAM through the amplifier circuit (1814) and the gate circuit (1815). This structure
realizes a high speed semiconductor memory device which can be applied to a desired
mapping method with a small area of occupation. |