The present invention relates generally to radio pagers, and more specifically to a sound alarm circuit for such radio pagers which generates an alert tone of escalating sound levels.
A radio pager having the capability of successively escalating the sound level of an alert tone is described in Japanese Patent Publication 63-252030 (Tokkaisho). According to the prior art technique, constant audio frequency pulses are modulated with a variable duty tone pattern that identifies particular incoming pages. The duty ratio of the tone pattern is successively increased to increase the sound level of the tone.
One serious disadvantage of the prior art technique is that since the sound level is controlled by the duty ratio of a tone pattern, the alert tone patterns as standardized by the Post Office Code Standardization Advisory Group (POCSAG) cannot be employed for escalating alert tones.
It is therefore an object of the present invention to provide a radio pager that enables internationally standardized alert tone patterns to be employed for alerting users with an escalating sound level.
According to the present invention, the radio pager comprises a receiver for receiving a paging signal containing a unique identifier identifying the own radio pager and an alert tone pattern. A pulse generating circuit generates audio-frequency pulses having a duty ratio increasing as a function of time in response to receipt of the paging signal. A modulating means is provided for modulating the variable duty pulses with the alert tone pattern for applying the modulated pulses to a loudspeaker.
The present invention will be described in further detail with reference to the accompanying drawings, in which:
A radio pager of the present invention as represented in Fig. 1 comprises a front end 2 for converting paging signals received by antenna 1 to baseband signals for coupling to a waveshaper 3. The output of waveshaper 3 Is applied to a decoder 4 in which the received signal is checked for a coincidence between a pager identifier contained in it and the one stored In a PROM (programmable read only memory) 5. On detecting a coincidence, decoder 4 alerts a sound alarm circuit 6 with a POCSAG (Post Office Code Standardization Advisory Group) alert tone signal having one of predetermined tone patterns or cadences. For example, one such cadence is a cyclic sequence of 7/8-second ON and 1/8-second OFF. Sound alarm circuit 6 modulates the tone signal with a variable duty pulse sequence and activates a loudspeaker 7. A reset switch 8 is connected to the decoder 4 to be operated when the user answers an incoming page.
As shown in Fig. 2, sound alarm circuit 6 comprises an AND gate 10 that is responsive to an enable signal from decoder 4 to pass high-frequency clock pulses from a clock source 9 to frequency dividers 11 and 12, and further to an up-counter 13 during the time the pager is being alerted. As shown in Fig. 3, frequency divider 11 divides the frequency of the clock to produce an output whose frequency determines the pitch of the alert tone, typically at 2.6 kHz, and frequency divider 12 divides that clock frequency so that its output determines the rate at which the duty ratio of the 2.6-kHz pulse sequence is varied. Typically, the duty ratio is stepwisely varied at 6-second intervals. The output of frequency divider 11 is applied to the up-counter 13 as a reset pulse so that its output represents a digital count value which continuously increments in response to the clock pulse until it rapidly drops to zero in response to the reset pulse. On the other hand, the output of frequency divider 12 is applied to a down-counter 15 to produce a decremental binary count value which represents the varying rate of the duty ratio. A monostable multivibrator 14 is provided for producing a pulse for clearing the contents of down-counter 15 as soon as the pager is alerted.
The digital output of down-counter 15 is applied to a binary-to-duty converter 16 which converts it to a digital value representing the duty ratio of the 2.6-kHz pulse sequence for each 6-second interval. In a typical example, binary-to-duty converter 16 successively generates outputs representing duty ratios of 12.5 %, 25 %, 33 % and 50 %. The outputs of binary-to-duty converter 16 and up-counter 13 are applied to a digital comparator 17 in which they are compared with each other to produce a high-level output when the digital value of counter 13 is greater than the output of binary-to-duty converter 16. It Is seen therefore that the output of comparator 17 is a sequence of constant-frequency pulses of a variable duty ratio which Increases stepwisely at 6-second intervals as shown in Fig. 3. From the tone quality standpoint, the maximum duty ratio is set 50 % as described above.
The output of comparator 17 is applied to an AND gate 18 to which a POCSAG tone pattern, say A-code pattern, is also applied. In this way, the variable duty 2.6 kHz pulse sequence is modulated by the POCSAG A-code pattern as shown in Fig. 4 and applied through an amplifier 19 to the speaker 7. Loudspeaker 7 has a narrow band of frequency response characteristic. This characteristic is sufficient to suppress the harmonic components of the modulated alert tone pulse which may otherwise cause changes in tone quality with variations of the duty ratio.
Therefore, the POCSAG tone pattern can be used for generating an alert tone with successively escalating sound levels.
Alternatively, the present invention can be further modified as shown in Fig. 5 in which the down-counter is replaced with an up-counter 31 and binary-to-duty converter 32 transforms the stepwisely incremental value of the output of counter 31 to a stepwisely incremental duty ratio. A flip-flop 30 is provided having a set input terminal connected to the output of frequency divider 11 and a reset input terminal connected to the output of programmable counter 34 whose program input is connected to the output of binary-to-duty converter 32. An AND gate 33 is responsive to the output of flip-flop 30 to pass the output of AND gate 10 to the clock Input of programmable counter 34. The output of flip-flop 30 is further applied to the reset input of programmable counter 34 and one input of AND gate 18.
As shown in Fig. 6, flip-flop 30 is triggered Into a high-level, set condition in response to each output pulse from frequency divider 11 to allow clock pulses from AND gate 10 to pass through AND gate 33 to the programmable counter 34. The latter produces a high-level output when the duty representing count value is reached and resets the flip-flop 30 to a low-level condition, producing a tone pulse having a stepwisely incremental duty ratio.
The foregoing description shows only one preferred embodiment of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which Is only limited by the appended claims. Therefore, the embodiment shown and described is only illustrative, not restrictive.