Clock with clock adjusting data memory

Abstract

 (Constitution) An oscillation circuit (1) has its frequency error stored as clock adjusting data in a memory such as EEPROM (8) or the like during a manufacture process by using a clock timer. The clock adjusting data stored in the memory (8) are adjusted in the adjusting sequence of the clock adjusting program, which is executed for a period of 12 hours.
The fast/slow adjustments are automatically accomplished to a correct time for the constant period by the clock adjusting data adjusted in the adjusting sequence.
(Effects)
It is possible to reduce the number of parts, improve the flexibility for design, standardize the clock circuit, eliminate the fast/slow adjusting member, and simplify the fast/slow adjustments.

Description

(Detailed Description of the Invention)

(Field of Industrial Application)

[0001] The present invention relates to a clock with a clock adjusting data memory, and more particularly, to a clock with a clock adjusting data memory having its clock adjusting data memory for storing an error of an oscillation frequency.

(Prior Art and Problems to Be Solved by the Invention)

[0002] In the prior art, some of carrying, portable and stationary devices such as cameras, video tape recorders, facsimilies, telephones or time recorders have built-in clock systems for indicating or printing the dates, hours, minutes and seconds in accordance with the purposes of photographing an object, recording a video image, transmit by facsimiles indicating the telephone rates, and managing when the employee enters and leaves the office. In case the device is exemplified by a camera for printing the film with the date and time when the object is taken, a clock equipped with a highly accurate oscillation source such as a crystal resonator is packaged in the camera so that a film exposing means such as a printing liquid crystal indicator is caused to flash with the date and time data which are outputted from the clock when the shutter is released. The camera may be packaged with not only the printing liquid crystal indicator but also a data indicating liquid crystal indicator for indicating the photographic data such as the frame numbers of the film. In either case, the liquid crystal indicator is driven with atemating current of 100 Hz or so, that is required to have only a low accuracy. Another oscillation source of the camera is one for the CPU, which is required to have characteristics different from those of the afore-mentioned oscillation source.

[0003] The device thus far described has difficulties such as the increase in the parts number due to the double oscillation sources, the reduction in the flexibility for design due to the increase in the parts number, the diversification of the clock circuit, and the increase in the numbers of individual adjustments due to the diversified clock circuit.

(Objects of the Invention)

[0004] The present invention has been conceived in view of the above-specified difficulties and has an object to provide a clock with a clock adjusting data memory, which is enabled to reduce the number of parts, improve flexibility for design standardize the clock circuit, eliminate the fast/slow adjusting member and simplify the individual fast/slow adjustments by providing the clock built in a device with a clock adjusting data memory which is stored with an error in the oscillation frequency and fast/slow adjusting data.

[0005] Another object of the present invention is to provide a clock with a clock adjusting data memory, which is enabled to reduce the clock adjusting data memory by storing the clock adjusting data in a non-volatile memory EEPROM disposed for another purpose.

(Means for Solving the Problems)

[0006] According to the present invention, there is provided a clock with a clock adjusting data memory, comprising: an oscillation circuit acting as the base of a timing function; an output means for outputting clock signal from the oscillation circuit; a clock adjusting data memory means for storing a characteristic error included in the oscillation circuit as clock adjusting data; and a clock adjusting means for adjusting the output of the output means on the basis of the clock adjusting data memory means.

(Operations)

[0007] An EEPROM 8, as shown in Fig. 1, is stored with the frequency error or period of crystal oscillation unit 1. Further stored are the clock data which are made in the manufacture process by a clock timer 16 in accordance with the clock adjusting program CLKADJ which is stored in ROM 9, as shown in Fig. 2. In case of the camera, the program for its control is interrupted at each predetermined period by a clock counter 6, as shown in Fig. 1, so that the clock adjustment is accomplished while the camera is in operation or standby by executing the clock adjusting program CLKADJ. If the adjustment data stored in the EEPROM 8 are frequency errors, the EEPROM 8 is stored, when the interruption period of the clock adjusting program CLKADJ is 12 hours, with the accumulated errors of 0.00003 x 43200 = 1.296 seconds for 43200 seconds corresponding to 12 hours of the frequency errors of 0.00003 seconds.

[0008] If the amount of adjustment is constant, e.g. 1 second and if its error is 0.023843 seconds, the interruption period is 11 hours and 39 minutes and is stored in the EEPROM 8.

(Embodiment)

[0009] One embodiment of the clock with the clock adjusting data memory according to the present invention will be described in detail in the following with reference to Figs. 1 and 2.

[0010] A clock with the clock adjusting data memory EQ₁, according to the present invention is constructed, as shown in Fig. 1, to include; a crystal oscillation unit 1 composed of a crystal resonator 2, a resistor 3, an inverter 4 and capacitors C₁ and C₂; a frequency divider 5 a clock counter 6; an LCD 7; an EEPROM 8; a ROM 9; and a RAM 10.

[0011] The crystal resonator 2 of the crystal oscillation unit 1 has its one end connected with one end of the resistor 3, the input terminal of the inverter 4 and one end of the capacitor C₁ which has the other end connected with the ground point. Moreover, the other end of the crystal resonator 2 is connected with the other end of resistor 3, the output terminal of the inverter and one end of the capacitor C₂ which has the other end connected with the ground point. Thus, an oscillation signal is outputted from the crystal oscillation unit 1 to the input terminal of the frequency divider 5 through a terminal 1a.

[0012] The output terminal of the frequency divider 5 is connected with the input terminal of the clock counter 6, which has its parallel output terminals connected with the LCD 7 having a function as output means. On the other hand, the clock counter 6 is connected with a CPU 13 through a data bus 11. Moreover, the RAM 10 and the ROM 9 stored with the clock adjusting program CLKADJ as a clock adjusting means are individually connected with the CPU 13 through the data bus 11.

[0013] On the other hand, the CPU 13 is connected through a timer data bus 12 with a clock timer 16, which can be disposed outside of the clock with the clock adjusting data memory EQ₁, and also with a terminal T₁ for outputting a signal having a period of 1 second, which is produced by dividing the frequency of the output of the crystal oscillation unit 1. Incidentally, the clock timer 16 is a meter which is used for rewriting the clock adjusting data of predetermined address in the EEPROM 8 of the clock with clock adjusting data memory EQ₁ during the manufacture process and for measuring the error of a clock composed of the crystal oscillation unit 1 and so on.

[0014] In the manufacture process, a signal having a period of 1 second is outputted from the terminal T₁ of the clock with the clock adjusting data memory EQ₁ when the clock timer 16 is connected with said clock with the clock adjusting data memory EQ₁. The clock counter 6 measures the period of that signal to calculate the difference from the designed intrinsic period. If the signal has a period of 1.00003 seconds although it should have a period of 1 second, for example, the difference of 0.00003 seconds is stored. Then, the accumulated value of the errors is calculated on the basis of the interrupt cycle of the clock adjusting program CLKADJ. More specifically, the afore-mentioned error is calculated in the manner of 0.00003 x 3600 x 12 = 1.296 seconds for 12 hours if the interruption cycle is 12 hours. This accumulated error is stored as the clock adjusting data in the EEPROM 8. It is natural that the correction data are headed by a sign + or -.

[0015] When the electric power is supplied to the completed camera a predetermined intialization program or the like in the CPU 13 is executed and the time is displayed.

[0016] After this, interrupts are required for the CPU 13 at every predetermined time interval by the clock counter 6. When the interrupt is required, the clock adjusting program CLKADJ, as shown in Fig. 2, is executed. Specifically, the present time is read at first from the clock counter 6 by the CPU 13. Next, the clock adjusting data are read from the EEPROM 8 so that the present time and the adjusting data are calculated together in the CPU 13. The present time is delayed by the adjusting data when it is advanced but is advanced, when it is delayed. After this operation, the arithmetically adjusted time is set in the clock counter 6 so that the correct time is indicated. Incidentally, since the time indication is usually at a unit of second even at the minimum, the value less than second is decided according to the required accuracy. If the higher time accuracy is required, the fraction less than second is stored in the RAM 10 so that the time may be adjusted after 12 hours including the fraction. These clock adjustments are accomplished in a remarkably short time so that the current consumption will hardly increase.

[0017] Moreover, the oscillation circuit in the foregoing embodiment uses the crystal as the resonator but may be exemplified by an IC or CR oscillation circuit.

[0018] The clock adjustment is accomplished for every 12 hours in the embodiment but may be accomplished at a constant time interval such as at 9 o'clock every morning. In this case, the amount of adjustment itself may enter as an error (for example, in case the time is set at 8 : 59). However, the required accuracy and the amount of adjustment are so considered in advance that they may be within ranges of no problem. If the amendments should raise a problem, the number of interruptions for the adjustment might be increased.

[0019] Moreover, the foregoing embodiment has been described in connection with the method, in which the EEPROM 8 is stored with the time amount of 0.00003 seconds to be adjusted. If however, the amount of adjustment has a constant period of 1 second and if the error is 0.023843 seconds, the interruption period is every 11 hours and 39 minutes, and this period may be stored in the EEPROM 8.

[0020] Means for detecting the ambient temperature may be provided so that the adjusting data in the foregoing embodiment may be used as those for the error which is caused due to the ambient temperature.

(Effects of the Invention)

[0021] The clock with the clock adjusting data memory according to the present invention is constructed to comprise; the oscillation circuit acting as the base of a timing function; the output means for outputting a clock signal from the oscillation circuit; the clock adjusting data memory means for storing a characteristic error included in the oscillation circuit as clock adjusting data; and the clock adjusting means for adjusting the output of the output means on the basis of the clock adjusting data memory means. Thus, the clock with the clock adjusting data memory has the effects capable of reducing the number of parts, improving the flexibility for design dom, standardizing the clock circuit, eliminating the fast/slow adjusting member, and simplyfying the fast/slow adjustments.

[0022] Another effect capable of reducing the clock adjusting data memory can be obtained by storing the clock adjusting data in the EEPROM which is provided for another purpose.

(Brief Description of the Drawings)

(Fig. 1)

[0023] A block diagram showing one embodiment of the clock with the clock adjusting data memory according to the present invention.

(Fig. 2)

[0024] 

[0025] A flow chart showing the clock adjusting program to be used in the clock with the clock adjusting data memory according to the present invention.

(Designations of Reference Numerals)

[0026] 

1

Crystal Oscillation Unit (Oscillation Circuit)

7

LCD (Output Means)

8

EEPROM (Clock Adjusting Data Memory Means)

CLKADJ

Clock adjusting Program (Clock Adjusting Means)

(Deisgnation of Document)   Drawings

[0027] (Fig. 1)
(Fig. 2)

Claims

1. A clock with a clock adjusting data memory, comprising;

an oscillation cicuit acting as the base of a timing function;

an output means for outputting a clock signal from said oscillation circuit;

a clock adjusting data memory means for storing a characteristic error included in said oscillation circuit as clock adjusting data; and

a clock adjusting means for adjusting the output of said output means on the basis of said clock adjusting data memory means.

2. A clock with a clock adjusting data memory as claimed in claim 1, wherein said clock adjusting data memory means is an EEPROM.

Drawing