(19)
(11) EP 0 511 573 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
16.02.1994 Bulletin 1994/07

(43) Date of publication A2:
04.11.1992 Bulletin 1992/45

(21) Application number: 92106800.3

(22) Date of filing: 21.04.1992
(51) International Patent Classification (IPC)5: G04G 3/02
(84) Designated Contracting States:
DE GB

(30) Priority: 19.04.1991 JP 88197/91

(71) Applicant: SEIKOSHA CO., LTD.
Chuo-ku, Tokyo (JP)

(72) Inventors:
  • Seki, Yoichi c/o Seikosha Co., Ltd.
    Yotsukaido-shi Chiba-ken (JP)
  • Saito, Hiroyuki c/o Seikosha Co., Ltd.
    Yotsukaido-shi Chiba-ken (JP)

(74) Representative: Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät 
Maximilianstrasse 58
80538 München
80538 München (DE)


(56) References cited: : 
   
       


    (54) Clock with clock adjusting data memory


    (57) (Constitution) An oscillation circuit (1) has its frequency error stored as clock adjusting data in a memory such as EEPROM (8) or the like during a manufacture process by using a clock timer. The clock adjusting data stored in the memory (8) are adjusted in the adjusting sequence of the clock adjusting program, which is executed for a period of 12 hours.
    The fast/slow adjustments are automatically accomplished to a correct time for the constant period by the clock adjusting data adjusted in the adjusting sequence.
    (Effects)
    It is possible to reduce the number of parts, improve the flexibility for design, standardize the clock circuit, eliminate the fast/slow adjusting member, and simplify the fast/slow adjustments.






    Search report