<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE ep-patent-document PUBLIC "-//EPO//EP PATENT DOCUMENT 1.4//EN" "ep-patent-document-v1-4.dtd"><!-- Disclaimer: This ST.36 XML data has been generated from A2/A1 XML data enriched with the publication date of the A3 document - March 2013 - EPO - Directorate Publication - kbaumeister@epo.org --><ep-patent-document id="EP92114140A3" file="EP92114140NWA3.xml" lang="en" doc-number="0513880" date-publ="19930113" kind="A3" country="EP" status="N" dtd-version="ep-patent-document-v1-4"><SDOBI lang="en"><B000><eptags><B001EP>..BECHDE....FRGB....LI..NL........................</B001EP><B005EP>R</B005EP><B053EP>This application was filed on 19 - 08 - 1992 as a divisional application to the application mentioned under INID code 60.</B053EP></eptags></B000><B100><B110>0513880</B110><B120><B121>EUROPEAN PATENT APPLICATION</B121></B120><B130>A3</B130><B140><date>19930113</date></B140><B190>EP</B190></B100><B200><B210>92114140.4</B210><B220><date>19830125</date></B220><B240 /><B250>en</B250><B251EP>en</B251EP><B260>en</B260></B200><B300><B310>343877</B310><B320><date>19820129</date></B320><B330><ctry>US</ctry></B330></B300><B400><B405><date>19930113</date><bnum>199302</bnum></B405><B430><date>19921119</date><bnum>199247</bnum></B430></B400><B500><B510><B516>5</B516><B511> 5G 07B  17/02   A</B511></B510><B540><B541>de</B541><B542>Mikroprozessorsysteme für Frankiermaschinenanordnungen</B542><B541>en</B541><B542>Microprocessor systems for electronic postage arrangements</B542><B541>fr</B541><B542>Systèmes à microprocesseur pour arrangements de machine à affranchir électronique</B542></B540><B560 /><B590><B598>1</B598></B590></B500><B600><B620><parent><pdoc><dnum><anum>86116058.8</anum><pnum>0231452</pnum></dnum><date>19830125</date></pdoc></parent></B620></B600><B700><B710><B711><snm>PITNEY BOWES INC.</snm><iid>00244950</iid><irf>57 696 a/fi</irf><adr><str>One Elmcroft</str><city>Stamford
Connecticut 06926-0790</city><ctry>US</ctry></adr></B711></B710><B720><B721><snm>Check, Frank T., Jr.</snm><adr><str>999 Camillia Way</str><city>San Jose, Ca. 95117</city><ctry>US</ctry></adr></B721></B720><B740><B741><snm>Lehn, Werner, Dipl.-Ing.</snm><sfx>et al</sfx><iid>00007471</iid><adr><str>Hoffmann, Eitle &amp; Partner,
Patentanwälte,
Postfach 81 04 20</str><city>81904 München</city><ctry>DE</ctry></adr></B741></B740></B700><B800><B840><ctry>BE</ctry><ctry>CH</ctry><ctry>DE</ctry><ctry>FR</ctry><ctry>GB</ctry><ctry>LI</ctry><ctry>NL</ctry></B840><B880><date>19930113</date><bnum>199302</bnum></B880></B800></SDOBI><abstract id="abst" lang="en"><p id="pa01" num="0001">A microprocessor system suitable for an electronic postage arrangement includes a microprocessor (10) having controllable address, data and control lines. First and second random access memories (20,21) are connected to the address, data and control lines. A printer (12) is coupled to the microprocessor. Feedback means (18) is provided to signal the printer setting to the microprocessor to enable updating of accounting data in the first and second random access memories.<img id="iaf01" file="imgaf001.tif" wi="76" he="99" img-content="drawing" img-format="tif" /></p></abstract><search-report-data id="srep" srep-office="EP" date-produced="" lang=""><doc-page id="srep0001" file="srep0001.tif" type="tif" orientation="portrait" he="297" wi="210" /><doc-page id="srep0002" file="srep0002.tif" type="tif" orientation="portrait" he="297" wi="210" /></search-report-data></ep-patent-document>