(19)
(11) EP 0 529 945 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
05.01.1994 Bulletin 1994/01

(43) Date of publication A2:
03.03.1993 Bulletin 1993/09

(21) Application number: 92307614.5

(22) Date of filing: 20.08.1992
(51) International Patent Classification (IPC)5: G11C 29/00, G06F 11/26, G06F 12/06
(84) Designated Contracting States:
DE FR GB IT NL

(30) Priority: 29.08.1991 US 752115

(60) Divisional application:
96100024.7 / 0716421

(71) Applicant: AT&T Corp.
New York, NY 10013-2412 (US)

(72) Inventor:
  • Raghavachari, Partha
    Chicago, Illinois 60613 (US)

(74) Representative: Buckley, Christopher Simon Thirsk et al
AT&T (UK) LTD., AT&T Intellectual Property Division, 5 Mornington Road
Woodford Green, Essex IG8 0TU
Woodford Green, Essex IG8 0TU (GB)


(56) References cited: : 
   
       


    (54) Method and apparatus for programmable memory control with error regulation and test functions


    (57) An electronic circuit (10) for controlling and testing up to eight banks (12) of RAMs (14₁ - 14n) includes a controller portion (20) for controlling accessing of the RAM banks to permit read and write operations to be carried out, and for initiating testing of the RAMs as well. The circuit (10) also includes a data path portion (22) for detecting parity errors in the data written to and read from the RAMs as well as for detecting errors which occur during testing initiated by the control portion. An interface portion (24) may also be provided to allow test commands, status information and error data to be communicated to and from the circuit (10) across a four-wire boundary scan bus.






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