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<!DOCTYPE ep-patent-document PUBLIC "-//EPO//EP PATENT DOCUMENT 1.1//EN" "ep-patent-document-v1-1.dtd">
<ep-patent-document id="EP92912544B1" file="EP92912544NWB1.xml" lang="en" country="EP" doc-number="0543974" kind="B1" date-publ="19961113" status="n" dtd-version="ep-patent-document-v1-1">
<SDOBI lang="en"><B000><eptags><B001EP>......DE....FRGB..IT....NL........................</B001EP><B003EP>*</B003EP><B005EP>J</B005EP></eptags></B000><B100><B110>0543974</B110><B120><B121>EUROPEAN PATENT SPECIFICATION</B121></B120><B130>B1</B130><B140><date>19961113</date></B140><B190>EP</B190></B100><B200><B210>92912544.1</B210><B220><date>19920612</date></B220><B240><B241><date>19930130</date></B241><B242><date>19950703</date></B242></B240><B250>en</B250><B251EP>en</B251EP><B260>en</B260></B200><B300><B310>9101837</B310><B320><date>19910614</date></B320><B330><ctry>SE</ctry></B330></B300><B400><B405><date>19961113</date><bnum>199646</bnum></B405><B430><date>19930602</date><bnum>199322</bnum></B430><B450><date>19961113</date><bnum>199646</bnum></B450><B451EP><date>19960402</date></B451EP></B400><B500><B510><B516>6</B516><B511> 6H 05K   1/00   A</B511><B512> 6H 05K   1/18   B</B512><B512> 6H 05K   3/46   B</B512></B510><B540><B541>de</B541><B542>LEITERPLATTE MIT  ABGESCHIRMTEN BEREICHEN SOWIE HERSTELLUNGSVERFAHREN EINER SOLCHEN LEITERPLATTE</B542><B541>en</B541><B542>A CIRCUIT BOARD HAVING  SHIELDED REGIONS AS WELL AS A METHOD OF MANUFACTURING SUCH A BOARD</B542><B541>fr</B541><B542>CARTE DE CIRCUITS IMPRIMES AYANT DES REGIONS BLINDEES, ET SON PROCEDE DE FABRICATION</B542></B540><B560><B561><text>EP-A- 0 146 241</text></B561><B561><text>EP-A- 0 312 682</text></B561><B561><text>GB-A- 2 120 861</text></B561></B560></B500><B700><B720><B721><snm>LEEB, Karl-Erik</snm><adr><str>Lillebo</str><city>S-130 40 Djurhamn</city><ctry>SE</ctry></adr></B721></B720><B730><B731><snm>TELEFONAKTIEBOLAGET LM ERICSSON</snm><iid>00213761</iid><irf>SEL 33015</irf><syn>LM ERICSSON, TELEFONAKTIEBOLAGET</syn><syn>ERICSSON, TELEFONAKTIEBOLAGET LM</syn><adr><str>
</str><city>126 25 Stockholm</city><ctry>SE</ctry></adr></B731></B730><B740><B741><snm>Delhage, Einar</snm><iid>00022632</iid><adr><str>Bergenstrahle &amp; Lindvall AB
Box 17704</str><city>118 93 Stockholm</city><ctry>SE</ctry></adr></B741></B740></B700><B800><B840><ctry>DE</ctry><ctry>FR</ctry><ctry>GB</ctry><ctry>IT</ctry><ctry>NL</ctry></B840><B860><B861><dnum><anum>SE9200408</anum></dnum><date>19920612</date></B861><B862>en</B862></B860><B870><B871><dnum><pnum>WO9222995</pnum></dnum><date>19921223</date><bnum>199232</bnum></B871></B870><B880><date>19930602</date><bnum>199322</bnum></B880></B800></SDOBI><!-- EPO <DP n="1"> -->
<description id="desc" lang="en">
<heading id="h0001"><u>Field of the invention</u></heading>
<p id="p0001" num="0001">The present invention relates to a circuit board having a conductive pattern and shielded regions as well as a method of manufacturing such a board.</p>
<heading id="h0002"><u>Background of the invention</u></heading>
<p id="p0002" num="0002">In electronic equipment for high frequencies and data signals having short transient times one portion in electronic equipment may interfere with the operation of other portions by the fact that the electromagnetical field will transfer signals over dielectric distances by induction. Such crosstalk will usually be dealt with by having the various portions of the equipment built into metal casings, which are electrically grounded and in the walls of which the electric field is short circuited, i.e. the casings will constitute shielded casings. The various portions are interconnected by coaxial cables. The signal being transferred on the coaxial cable may be purged from undesirable frequencies by means of special filters. The disadvantages of such shielded casings are partly that they are relatively costly, partly they are spaceconsuming. Another problem is that it is often difficult to provide sufficiently electromagnetically closed shields between the various portions of the electronic equipment in the case where one wants to integrate it on one single circuit board.</p>
<p id="p0003" num="0003">In conventional pattern boards often regions of the circuit board are surrounded by an etched and grounded frame incorporated in and surrounding the rest of the conductive pattern and further a ground plane is attached to the opposite side of the circuit pattern board. By soldering a metal shield on said grounded frame a region, which is fairly well but not completely shielded, is obtained. The problem in this case is that the electromagnetic radiation will leak laterally between the grounded frame and the ground plane in the laminate thus formed. This radiation can be partly confined by having holes drilled and metallized, which connect the ground plane and the grounded frame. The radiation leakage, however, may only be restricted in a certain amount in this way, since said holes cannot be located too closely to each other since this would<!-- EPO <DP n="2"> --> impart a mechanical weakening of the laminate. Producing metallized holes in this way is, in addition, costly and constitutes a source of errors. Said method is particularly unsuitable for circuit boards intended for cheap and little space consuming surface mounting where holes are not required for the attachment of component legs but only as a connection between various conductive layers.</p>
<heading id="h0003"><u>Prior Art</u></heading>
<p id="p0004" num="0004">From the European patents 0 288 767 and 0 337 331 and the U.S. patent 4 673 904 it is previously known to prepare conductive patterns, where the conductors on all sides are enclosed by dielectrics and ground planes. The disadvantage of these prior methods is that a multitude of selective metal patterns and electrically insulating patterns must be applied to a substrate in several sequential procedural steps what makes these methods complicated and the risk of having a bad manufacturing output is obvious. Another problem of this technique is that it is based on a deposition of metal on the substrate surface and that such deposited metal layers present a bad ductility. Further, this method is not compatible with what is generally established within the technique of manufacturing etched circuit pattern boards.</p>
<heading id="h0004"><u>Summary of the invention</u></heading>
<p id="p0005" num="0005">The purpose of the present invention is to provide a new and significantly simpler method for removing the disadvantages discussed above in the technique known up to this date, wherein conductive patterns are produced by etching a metal foil adhesively bonded to the substrate according to the established method of circuit pattern board manufacture and wherein in many cases rolled metal foil can be used which will produce a certain stretchability and flexibility in the manufactured card.</p>
<p id="p0006" num="0006">This purpose is achieved with a circuit board and a method of the kind indicated above having the characteristics set out in the appended claims.</p>
<p id="p0007" num="0007">Thus a circuit board having a conductive pattern and shielded regions is provided comprising a first laminate of a substrate having a conductive pattern of signal conductors and ground conductors on one side and optionally an entirely covering copper foil on the other side, this first laminate<!-- EPO <DP n="3"> --> being laminated with the side having a conductive pattern to another second laminate comprising a second substrate and a copper foil arranged on the side facing away from the first laminate, windows or apertures being cut in the substrate of the second laminate and etched away from its copper foil respectively in order to enable mounting of components to the conductive pattern inside the windows, and that a metal layer is arranged to electrically connect the optional, entirely covering foil of the first laminate with the ground conductors of the conductive pattern and the foil of the second laminate and also to cover the whole side of the first laminate where the optional entirely covering copper foil may be located, at least when such an optional copper foil is not arranged on this side.</p>
<p id="p0008" num="0008">According to advantageous embodiments of the circuit board of the invention the ground conductors of the conductive pattern are prepared with protruding portions such as contact tabs projecting past the edge of the substrate and the copper foil of the second laminate may likewise project past the second substrate edge in order to make a good contact with the metal layer connecting the ground planes of the board.</p>
<p id="p0009" num="0009">The method for the manufacture of the circuit boards thus comprises the following steps:
<ul id="ul0001" list-style="none" compact="compact">
<li>that a first electrically insulating substrate, which on one of the sides thereof may be coated with a conductive layer, such as a first copper foil, is cut, for instance by means of a laser beam or a water jet, to give the first substrate, together with the possible conductive layer, a desired outer contour or profile,</li>
<li>whereafter another, first conductive layer, such as a first copper foil, is applied to, for instance laminated to, the other, first side of the first substrate to entirely cover said first side and</li>
<li>the first conductive layer is etched to produce a conductive pattern comprising signal conductors and ground conductors on the first side of the first substrate and</li>
<li>that a second electrically insulating substrate is cut to give it a desired outer contour or profile and windows or apertures through the thickness of said substrate and that it is coated with, for instance laminated to, a second conductive<!-- EPO <DP n="4"> --> layer, such as a second copper foil, on one of its sides, the foil covering all of this first side,</li>
<li>whereafter windows are etched in the second conductive layer corresponding to said windows or apertures cut in said second substrate,</li>
<li>whereafter the second laminate formed in this way from the second substrate and the second conductive layer is placed on top of the first laminate in such a way that the second conductive layer of the second laminate is turned away from the first laminate and the first conductive layer having the conductive pattern of the first laminate is engaged with the other, second side of the second laminate and the two laminates are intimate attached to each other, for instance adhesively bonded to each other, and</li>
<li>that a conductive layer such as a metal layer is applied to at least the marginal portions of that second side of the first laminate, which is turned away from the second laminate and thus may have a conductive layer, and the edges or marginal portions of the two laminates in order to electrically connect the said side of the first laminate, ground conductors of the conductive pattern on the first laminate and the third conductive layer on the second substrate, the application of this conductive metal layer being at least partly accomplished by means of thermal spraying of a low-melting metal, for instance tin or an alloy thereof,</li>
<li>whereafter components are mounted in the windows or apertures in the second laminate to the circuit pattern of the first laminate.</li>
</ul></p>
<p id="p0010" num="0010">According an advantageous embodiment of the invention metal caps are provided over the windows of one of the laminates, said metal caps being soldered or clamped firmly against the copper foil of the substrate in order to shield the window regions.</p>
<p id="p0011" num="0011">According to another advantageous embodiment of the invention portions of the optional copper foil of the side of the first laminate, which is opposite to the side having the conductive pattern, are etched away and masked against metal coating in order to enable access to the conductive pattern from this side.</p>
<heading id="h0005"><u>Short description of the figures</u></heading>
<p id="p0012" num="0012">Embodiments of the invention will now by way of example be<!-- EPO <DP n="5"> --> described in more detail with reference to the accompanying drawings, in which
<ul id="ul0002" list-style="none" compact="compact">
<li>Fig. 1 is a perspective view of two laminates comprised in the circuit board according to the invention,</li>
<li>Fig. 2 is a cross sectional view of the finished circuit board,</li>
<li>Fig. 3 is a cross sectional view of an alternative embodiment of the finished circuit board,</li>
<li>Fig. 4 is a cross sectional view of the finished, mounted circuit board,</li>
<li>Fig. 5 is a cross sectional view of a connecting portion along the lines V-V in Fig. 1,</li>
<li>Fig. 6 is a cross sectional view illustrating ground connection in a component mounting region,</li>
<li>Fig. 7 is a cross sectional view of an embodiment of a multilayer board and two laminates,</li>
<li>Figures 8 to 13 illustrate different steps in the preparation of the two laminates,</li>
<li>Figures 14 and 15 illustrate the assembly of the laminates and the final metallization step and</li>
<li>Figures 16 and 17 illustrate alternative methods of attaching metal caps.</li>
</ul></p>
<heading id="h0006"><u>Description of preferred embodiments</u></heading>
<p id="p0013" num="0013">In the figures the thicknesses illustrated of the substrates and the foils are highly exaggerated in order to clarify the invention.</p>
<p id="p0014" num="0014">In Fig. 1 a dielectric first substrate 1 is shown which is contour cut by laser or a water jet and on which a conductive circuit pattern is located. The conductive pattern is etched from a conductive layer located on and attached to one side of the substrate 1, such as a copper foil adhesively bonded to said substrate, and it comprises conductors 2 for signals and ground conductors 3. The ground conductors 3, may as is shown in the Figure, be located at the marginal portion of the substrate 1, in order to form a grounded frame surrounding the signal conductors 2. The conductive pattern 2, 3 may suitably be etched through a resist mask in the conventional way. From the ground conductors 3 contact tabs 5 project past the edge of substrate 1, these contact tabs being connected to or being part of the<!-- EPO <DP n="6"> --> ground conductors 3.</p>
<p id="p0015" num="0015">Preferably another conductive metal layer such as a copper foil 4 is adhesively bonded to the other side of the substrate 1 and covers the entire surface of this other side.</p>
<p id="p0016" num="0016">A second laminate comprises a second substrate 6, which is cut by laser or a water jet and on which a metal layer such as a copper foil 7 is adhesively bonded or otherwise attached. The copper foil 7 extends past the edges of the substrate 6 to form a free copper marginal portion and portions of the copper foil 7 are etched away on locations corresponding to the windows 8 cut in the substrate 6 to form windows or apertures passing through the thickness of the second laminate.</p>
<p id="p0017" num="0017">In Fig. 2 the two laminates of Fig. 1 are illustrated adhesively or otherwise bonded to each other in such a way that their patterns fit together, that is the circuit pattern 2, 3 of the first laminate is positioned correctly with respect to the windows 8 in the second laminate. They are arranged with the side of the substrate 1 having the circuit pattern brought into engagement with the surface of the second substrate 6 which is not coated with a metal foil. On the side, which is opposite to the windows 8, of the composite laminate illustrated in Fig. 2, a conductive layer is applied, preferably a layer 10 of tin or an alloy thereof, which is thermally sprayed such as by means of flame spraying and it will electrically connect the portions which are intended to be connected to a reference or ground potential, i.e. the entirely covering foil 4 on the other, second side of the first laminate, the tabs 5 extending from the grounded conductor frame 3 and the metal foil 7 bonded to the outer side of the second laminate. The bottom conductive layer 4 could in some cases be omitted but is generally preferred since it will ensure a could adhesion between the bottom of the completed circuit board and the thermally sprayed metal layer 10. Also, for an easy application the metal layer 10 covers all of the bottom surface of the composite board, but this is generally not required for the electrical shielding. The metal layer may thus, as is illustrated in Fig. 3, cover only the edge regions of the completed board, also in order to perform the electrical connection mentioned above.</p>
<p id="p0018" num="0018">The two laminates illustrated in Fig. 1 are in the composite<!-- EPO <DP n="7"> --> unit of Figs. 2 and 3 fitted to each other in such a way that the inner edge of the windows 8 will enclose component mounting regions of the side having the conductive pattern of the substrate 1.</p>
<p id="p0019" num="0019">At the locations where the second substrate 6 and the copper foil 7 of the second laminate cover the circuit pattern of the first laminate thus the circuit pattern will be enclosed between two ground planes 4, 7.</p>
<p id="p0020" num="0020">In the windows cut in the substrate 6 and in the copper foil 7 of the second laminate electronic components 12 such as capacitors are intended to be mounted to the conductive pattern 2 on the inner side of the first laminate by means of surface mounting technique, see Fig. 4. After the component mounting these regions will be shielded by soldering a pressed metal cap, at 16, to the copper foil 7 on top of the second laminate, in such a way that the cap 14 will cover all of the window 8. Instead of soldering the cap 14 can be clamped or otherwise attached and electrically connected to the metal foil 7 covering the outer surface of the second laminate as will be further illustrated hereinafter.</p>
<p id="p0021" num="0021">The regions for component mounting may be connected through portions, as is illustrated in Fig. 1 in the centrally located narrow portion, where elongated, band or strip shaped signal paths 40 of the signal conductors 2 are enclosed by the adhesively bonded substrates 1, 6 which constitute a dielectric, which in turn is enclosed by the ground planes 7, 4, which in turn are connected to each other by the tin layer 10, as has been mentioned above, compare Fig. 5. In this case the signal paths 40 may be surrounded at their longitudinal, lateral edges by portions 41, 42 of the tin layer 10. In order to accomplish this elongated windows 45 or apertures are arranged having their longitudinal edges at a suitable distance from the signal paths, at both of the edges of the signal paths 40 or at only one 43 of their edges, if the other edge 44 is located at the same suitable distance from the edge of the circuit board, these windows being made both in first laminate and in the substrate 6 of the second laminate, leaving the copper foil on the second substrate 6 to cover these windows. In this way the signal paths will be effectively shielded, also from each other with a<!-- EPO <DP n="8"> --> constant impedance along their lengths between or in parallel with these windows 45. Inside the windows 45 the tin metal layer 10 will contact those left portions of the top copper foil 7. Also the edge profile of the finished circuit board may have the same steplike shape as illustrated for instance in Fig. 2, the edge of the second substrate 6 projecting past the edge of the first laminate inside the windows.</p>
<p id="p0022" num="0022">If an electrically grounded surface 18 is desired inside the grounded frame 3 and within the signal conductor pattern 2 a hole 20 is surface cut by means of laser or a water jet in the first substrate 1 of the first laminate, see Fig. 6, before the lamination of the first copper foil for the conductor pattern, and the corresponding parts of the bottom copper foil 4 on this first substrate are etched away. The copper foil, in which the conductive pattern is etched, will then cover the hole 20 and the thermally sprayed tin layer 10 will connect the ground planes 7, 18, and 4, as is illustrated in Fig. 6.</p>
<p id="p0023" num="0023">The method described above is suited for single conductive layers. If several conductive planes or intersections are required this is suitably accomplished by means of screen printing of electrically insulating and conducting mixtures of artificial resins or plastics, so called polymer thick film technique. Such a method for the manufacture of thin continuous substrate strips is described in the Swedish Patent 455 148, which is incorporated herein as a reference.</p>
<p id="p0024" num="0024">The copper foil 4 which may be arranged on the side opposite the side having the circuit pattern of the substrate 1 of the first laminate can be etched and masked against metallization in order to provide access to the circuit also from this side. Such regions may then be shielded by electrically closed metal caps 26, as is illustrated in Fig. 7, wherein an embodiment is illustrated consisting of two laminates, combined with a multilayer board 22 located on top of the above mentioned conductive pattern comprising the signal and ground conductors 2, 3. The contacting of the conductive planes incorporated in the multilayer board and the conductors 2, which have been etched on the substrate 1, is accomplished by means of metallized holes 24. In this case the metal layer 10 on the bottom and edges of the circuit board and the metal layer inside<!-- EPO <DP n="9"> --> and at top and bottom of the through-holes may advantageously be prepared at the same time by metal plating, as is conventionally used in metallization of through-holes in multilayer circuit pattern boards.</p>
<p id="p0025" num="0025">The multilayer board 22 is prepared according to conventional circuit board technique and the other laminates are prepared as has been described above. The laminates are drilled and the holes are coated according to prior multilayer board methods wherein the regions of the ground plane 4 of the lower laminate of Fig. 7, where the coated hole 24 will be produced, is etched away and the hole 24 is connected to the signal conductors of the multilayer board 20. The ground planes 4, 7 are contacted through a simultaneously deposited metal layer 10, as has already been mentioned. In this embodiment shield caps 14, 26 are mounted at the ground planes 7, 10 by means of soldering joints 16 and 28 respectively in order to shield the circuit space completely.</p>
<p id="p0026" num="0026">Circuit boards can thus be laminated with composite devices as has been described above and the conductors thereof are electrically connected by drilled and metal coated holes in regions, where the copper foil have been etched away and the metallization has been masked.</p>
<p id="p0027" num="0027">An example of the method according to the invention for the preparation of circuit boards having a conductive pattern and shielded regions of the kind illustrated in Fig. 2 will now be described in more detail with reference to Figures 8 - 15.</p>
<p id="p0028" num="0028">A laminate of a substrate 1 of 0.2 mm thick glass fibre reinforced plastics is coated with 0.035 mm thick copper foil 4 on one side and is contour cut by means of laser, see Fig. 8.</p>
<p id="p0029" num="0029">A laminate cut in this way is laminated in a hydraulic press provided with a suitable heating to a larger copper foil 11, similarly having a thickness 0.035 mm. The same adhesive is used as a bonding agent, see Fig. 9.</p>
<p id="p0030" num="0030">The substrate coated on both sides is then coated by dipping in a photo resist. A pattern is exposed and is etched in the copper foil 11, this pattern constituting signal conductors 2 and ground planes 3. At suitable places contact tabs or contact tongues 5 project past the edge of the substrate 1, see Fig. 10.<!-- EPO <DP n="10"> --></p>
<p id="p0031" num="0031">The laminate a prepared in this way according to Figs. 8 - 10 constitutes a first intermediate product, compare Fig. 14.</p>
<p id="p0032" num="0032">The second substrate 6, similarly consisting of 0.2 mm thick glass fibre reinforced plastics but not coated with a copper foil on any of its sides is contour cut by means of laser. The substrate 6 cut in this way is 0.5 to 1 mm larger than the first intermediate product a, this dimension being chosen to have the same order of magnitude as the thicknesses of the laminates in order to make the marginal portions of the sprayed metal layer 10 extend not perpendicularly to the surfaces of the laminates and at a small angle of about 5 to 45 degrees, see Fig. 11.</p>
<p id="p0033" num="0033">The cut substrate 6 is laminated to a larger copper foil 7, which thus will project past the edges of the substrate 6. The thickness of the copper foil is as before 0.035 mm. The projecting portion of the copper foil 7 may then also have a width of the same magnitude of order as the thickness of the laminates, see Fig. 12.</p>
<p id="p0034" num="0034">The laminate 6, 7 formed in this way is coated with a photo resist by dipping and is exposed and etched in order to form windows 8, see Fig. 13.</p>
<p id="p0035" num="0035">The laminate prepared in this way constitutes a second intermediate product b, compare Fig. 14.</p>
<p id="p0036" num="0036">The first and second intermediate products a, b are adhesively bonded to each other in such a way that their contours coincide in the desired way, see Fig. 14. The bonding is accomplished in a heated hydraulic press.</p>
<p id="p0037" num="0037">The bonded product is flame sprayed with tin 10 on the side opposite to the side having the windows 8 and the conductive pattern, see Fig. 15, whereby the ground planes 4, 5 and 7 are electrically connected. In this operation the contact tabs 5 of the grounded frame 3 and the portion of the foil 7 projecting past the substrate edge function to ensure a good electrical contact with the metal layer 10. Before spraying of the metal layer 10 it is important that the copper foil and the contact tabs should have been cleaned from remaining adhesive.</p>
<p id="p0038" num="0038">In Figs. 16 and 17 two alternative methods of attaching the metal caps 14 over the component mounting areas are illustrated, which methods could also be used for the metal caps on the bottom side of the finished circuit board. Thus in the<!-- EPO <DP n="11"> --> construction illustrated in Fig. 16 bolts 31 are inserted through holes in the metals caps 14 and the thickness of the circuit board and the force from nuts 32 tightened on the bolts 31 presses the metal cap 14 onto the top copper foil 7. In the alternative illustrated in Fig. 17 the metal cap 14 is pressed to contact the copper foil 7 along the periphery thereof by a bent metal wire 32 which is inserted through holes in the thickness of the circuit board. An intermediate element 33 such as a wedge shaped means maybe used between the bent element 32 and the top portion of the metal cap 14 to ensure a correct pressing force.</p>
<p id="p0039" num="0039">The invention can be modified by anyone skilled in the art. Thus for instance instead of localized contact tabs 5 projecting from the outer margin of the conductive pattern the tabs can be continuous and extend all the way along some or all of the edges of the first substrate 1. Also, the projecting margin of the conductive layer 7 on top of the second substrate 6 may not be continuous and comprise tab portions, but this would reduce the adhesive force of the metal layer 10.</p>
</description><!-- EPO <DP n="12"> -->
<claims id="claims01" lang="en">
<claim id="c-en-01-0001" num="0001">
<claim-text>A circuit board having an electrically conductive pattern and electrically shielded regions, <b>characterized in</b> that a first laminate comprising an electrically insulating first substrate (1) having a first conductive layer, the first layer comprising an electrically conductive pattern of signal conductors (2) and ground conductors (3) and located on one, first side of the first laminate, is laminated, with the first side having the conductive pattern to another laminate comprising an electrically insulating second substrate (6) and a second electrically conductive layer, in particular a copper foil (7), arranged on the first side of the second substrate (6), this first side being turned away from the first laminate, that windows (8) or through-holes are arranged through the thickness of the second laminate, in order to enable mounting of components (12) to the conductive pattern of the first laminate inside the windows (8) or through-holes, and that another, third conductive layer (4, 10), in particular a metal layer, is arranged to cover the edges or marginal portions of the two laminates to electrically connect the ground conductors (3) of the conductive pattern and the conductive layer (7) of the second laminate.</claim-text></claim>
<claim id="c-en-01-0002" num="0002">
<claim-text>A circuit board according to claim 1, <b>characterized in</b> that the windows (8) or through-holes in the second laminate are cut in the substrate (6) of the second laminate and are etched away from the second conductive layer (7).</claim-text></claim>
<claim id="c-en-01-0003" num="0003">
<claim-text>A circuit board according to one of claims 1 - 2, <b>characterized in</b> that the third conductive layer (4, 10) comprises a fourth conductive layer, in particular a copper foil (4), applied to only the second side of the first laminate and a fifth conductive layer covering at least the edges of the circuit board.</claim-text></claim>
<claim id="c-en-01-0004" num="0004">
<claim-text>A circuit board according to one of claims 1 - 3, <b>characterized in</b> that conductive caps (14, 26), in particular metal caps, are soldered or clamped to the second conductive layer (7) of the second laminate in order to cover the windows (8).</claim-text></claim>
<claim id="c-en-01-0005" num="0005">
<claim-text>A circuit board according to one of claims 1 - 4, <b>characterized in</b> that the ground conductors (3) of the<!-- EPO <DP n="13"> --> conductive pattern of the first laminate comprise portions, in particular contact tabs (5), projecting past the edge of the substrate (1) of the first laminate in order to contact the third conductive layer (4, 10) connecting the other conductive layer and the ground conductors (3) of the conductive pattern.</claim-text></claim>
<claim id="c-en-01-0006" num="0006">
<claim-text>A circuit board according to one of claims 1 - 5, <b>characterized in</b> that the second conductive layer (7) of the second laminate (6) projects past the edge of the substrate of the second laminate in order to contact the third conductive layer (4, 10) connecting the other conductive layer and the ground conductors (3) of the conductive pattern.</claim-text></claim>
<claim id="c-en-01-0007" num="0007">
<claim-text>A circuit board according to one of claims 1 - 6, <b>characterized in</b> that the second substrate (6) is slightly larger than the first substrate (1) and that the first and second substrates are arranged in relation to each other in such a way that a margin of the second substrate (6) extends past the edge of the first substrate (1) along the edges of the circuit board.</claim-text></claim>
<claim id="c-en-01-0008" num="0008">
<claim-text>A circuit board according to claim 7, <b>characterized in</b> that the margin has a width of essentially the same size as the thickness of the substrates or more.</claim-text></claim>
<claim id="c-en-01-0009" num="0009">
<claim-text>A circuit board according to one of claims 1 - 8, <b>characterized by</b> windows (20) or through-holes in the first substrate, regions or areas (18) of the first conductive layer being left on top of these windows (20) or through-holes, the third conductive layer (4, 10) being arranged to connect electrically the edges of the conductive layers inside the windows (20) or through-holes and the regions or areas (18) to form grounded areas inside the conductor pattern in the first conductive layer.</claim-text></claim>
<claim id="c-en-01-0010" num="0010">
<claim-text>A circuit board according to claim 3, <b>characterized by</b> windows (20) or through-holes in the first substrate, also passing through the fourth conductive layer (4), regions or areas (18) of the first conductive layer being left on top of the windows (20) or through-holes, and the third conductive layer (4, 10), particularly the fifth conductive layer (10) being arranged to connect electrically the edges of the conductive layers inside the windows (20) or through-holes and the regions or areas (18) to form grounded areas inside the<!-- EPO <DP n="14"> --> conductor pattern in the first conductive layer.</claim-text></claim>
<claim id="c-en-01-0011" num="0011">
<claim-text>A circuit board according to one of claims 1 - 10 having bandshaped or stripshaped conductors (40) connecting one part of the circuit board to another part thereof, <b>characterized in</b> that windows (45) are made located adjacent to the bandshaped or stripshaped conductors (40) through the first laminate and through the substrate (6) of the second laminate and that the second conductive layer (7) extends over these windows (45).</claim-text></claim>
<claim id="c-en-01-0012" num="0012">
<claim-text>A circuit board according to claim 11, <b>characterized in</b> that over a considered length of the bandshaped or stripshaped conductors (40) there is an edge either of the circuit board or of the windows (45) made through the first laminate and through the substrate (6) of the second laminate on both sides of this length, the distance from the edge of the conductor (40) to the edge of the circuit board or the windows (45) being substantially constant and equal to each other over this considered length.</claim-text></claim>
<claim id="c-en-01-0013" num="0013">
<claim-text>A circuit board according to one of claims 1 - 12, <b>characterized in</b> that the substrates (1, 6) are made from glass fibre reinforced plastics.</claim-text></claim>
<claim id="c-en-01-0014" num="0014">
<claim-text>A method of manufacturing a circuit board having an electrically conductive pattern and electrically shielded regions, <b>characterized in</b>
<claim-text>that a first, electrically insulating substrate (1) is given a desired outer contour or profile,</claim-text>
<claim-text>that a first, electrically conductive layer comprising a conductor pattern including signal conductors (2) and ground conductors (3) is produced on a first side of the first substrate (1),</claim-text>
<claim-text>that a second, electrically insulating substrate (6) is given a desired outer contour or profile and windows (8) or through-holes are produced through the thickness of the substrate (6),</claim-text>
<claim-text>that a second, electrically conductive layer (7) is produced on a first side of the second substrate (6),</claim-text>
<claim-text>whereafter windows are produced in the second conductive layer (7) corresponding to the windows (8) or through-holes in the second substrate (6),</claim-text>
<claim-text>whereafter the second laminate formed in this way from the second substrate (6) and the second conductive layer (7) is<!-- EPO <DP n="15"> --> placed on top of the first laminate in such a way that the second conductive layer (7) of the second laminate is turned away from the first laminate and the first conductive layer (11) having the conductive pattern of the first laminate is engaged with the other, second side of the second laminate and the two laminates are attached to each other, and</claim-text>
<claim-text>that a third, electrically conductive layer (4, 10) is applied to that second side of the first laminate, which is turned away from the second laminate, and the edges or marginal portions of the two laminates in order to electrically connect the ground conductors (3) of the conductive pattern on the first laminate and the second conductive layer (7) on the second substrate,</claim-text>
<claim-text>whereafter components (12) are mounted in the windows (8) or through-holes in the second laminate to the circuit pattern of the first laminate.</claim-text></claim-text></claim>
<claim id="c-en-01-0015" num="0015">
<claim-text>A method according to claim 14, <b>characterized in</b> that the first insulating substrate (1) on one of the sides thereof is coated with a fourth, electrically conductive layer (4), before it is given the desired contour or profile.</claim-text></claim>
<claim id="c-en-01-0016" num="0016">
<claim-text>A method according to claim 15, <b>characterized in</b> that the third conductive layer (4, 10) comprises a fifth, electrically conductive layer (10) applied at least to the marginal portions of that second side of the first laminate, which is turned away from the second laminate and thus has the fourth conductive layer (4).</claim-text></claim>
<claim id="c-en-01-0017" num="0017">
<claim-text>A method according to one of claims 15 - 16, <b>characterized in</b> that portions of the fourth conductive layer (4) on the side opposite to the side having the conductive pattern of the first laminate are etched away and are not covered by any electrically conductive coating in order to enable access to the conductive pattern through the first laminate.</claim-text></claim>
<claim id="c-en-01-0018" num="0018">
<claim-text>A method according to one of claims 14 - 17, <b>characterized in</b> that the first conductive layer (11) is etched to produce the conductive pattern including the signal conductors (2) and ground conductors (3).</claim-text></claim>
<claim id="c-en-01-0019" num="0019">
<claim-text>A method according to one of claims 14 - 18, <b>characterized in</b> that the windows are etched in the second<!-- EPO <DP n="16"> --> conductive layer (7).</claim-text></claim>
<claim id="c-en-01-0020" num="0020">
<claim-text>A method according to one of claims 14 - 19, <b>characterized in</b> that the two laminates are adhesively bonded to each other.</claim-text></claim>
<claim id="c-en-01-0021" num="0021">
<claim-text>A method according to one of claims 14 - 20, <b>characterized in</b> that on top of the windows (8) or through-holes metal caps (14, 26) are soldered or clamped to the second conductive layer (7) of the second substrate (6).</claim-text></claim>
<claim id="c-en-01-0022" num="0022">
<claim-text>A method according to one of claims 14 - 21, <b>characterized in</b> that the third conductive layer (4, 10) is at least partly applied by means of thermal spraying of a low-melting metal, in particular tin or an alloy thereof.</claim-text></claim>
<claim id="c-en-01-0023" num="0023">
<claim-text>A method according to one of claims 14 - 22, <b>characterized in</b> that windows (20) or through-holes are also made in the first substrate (1) where these windows or through-holes are protected from obtaining any conductive layer on the other, second side of the first laminate, in order to enable access to the conductive pattern through the first laminate.</claim-text></claim>
<claim id="c-en-01-0024" num="0024">
<claim-text>A method according to claim 23, <b>characterized in</b> that portions, corresponding to the windows or through-holes in the first substrate, of a fourth, electrically conductive layer (4) on the side opposite to the side having the conductive pattern of the first laminate, are etched away and masked against any electrically conductive coating.</claim-text></claim>
<claim id="c-en-01-0025" num="0025">
<claim-text>A method according to one of claims 14 - 24, <b>characterized in</b> that other circuit pattern boards are laminated to the first laminate and that holes drilled and coated with an electrically conductive layer to connect conductors of the other circuit pattern boards to the circuit pattern on the first laminate.</claim-text></claim>
<claim id="c-en-01-0026" num="0026">
<claim-text>A method of manufacturing circuit boards having an electrically conductive pattern and shielded regions,<br/>
<b>characterized in</b>
<claim-text>that a first, electrically insulating substrate (1), which on one of the sides thereof may be coated with an electrically conductive layer (4), in particular a copper foil, is cut to give the first substrate (1), together with the possible conductive layer (4), a desired outer contour or profile,</claim-text>
<claim-text>whereafter another first, electrically conductive layer (11),<!-- EPO <DP n="17"> --> in particular a copper foil, is applied to, in particular laminated to, the other, first side of the first substrate (1) to entirely cover the first side and</claim-text>
<claim-text>the first conductive layer (11) is etched to produce a conductive pattern comprising signal conductors (2) and ground conductors (3) on the first side of the first substrate (1) and</claim-text>
<claim-text>that a second, electrically insulating substrate (6) is cut to give it a desired outer contour or profile and windows (8) or through-holes through the thickness of this substrate (6) and that it is coated with, in particular laminated to, a second, electrically conductive layer (7), in particular a copper foil, on one of its sides, the first thereof,</claim-text>
<claim-text>whereafter windows are etched in the second conductive layer (7) corresponding to the windows (8) or through-holes cut in the second substrate (6),</claim-text>
<claim-text>whereafter the second laminate formed in this way from the second substrate (6) and the second conductive layer (7) is placed on top of the first laminate in such a way that the second conductive layer (7) of the second laminate is turned away from the first laminate and the first conductive layer (11) having the conductive pattern of the first laminate is engaged with the other, second side of the second laminate and the two laminates are adhesively bonded to each other, and</claim-text>
<claim-text>that an electrically conductive layer (10), in particular a metal layer, is applied to at least the marginal portions of that second side of the first laminate, which is turned away from the second laminate and thus may have a conductive layer (4), and the edges or marginal portions of the two laminates in order to electrically connect the side of the first laminate, ground conductors (3) of the conductive pattern on the first laminate and the third conductive layer (7) on the second substrate,</claim-text>
<claim-text>whereafter components (12) are mounted in the windows (8) or through-holes in the second laminate to the circuit pattern of the first laminate.</claim-text></claim-text></claim>
</claims><!-- EPO <DP n="18"> -->
<claims id="claims02" lang="de">
<claim id="c-de-01-0001" num="0001">
<claim-text>Schaltungsplatine mit einem elektrisch leitenden Muster und elektrisch abgeschirmten Bereichen, <b>dadurch gekennzeichnet, daß</b> ein erster Schichtaufbau, umfassend ein elektrisch isolierendes erstes Substrat (1) mit einer ersten leitenden Schicht, wobei die erste leitende Schicht ein elektrisch leitendes Muster von Signalleitern (2) und Masseleitern (3) umfaßt und sich auf einer ersten Seite des ersten Schichtaufbaus befindet, mit der ersten Seite, die das leitende Muster aufweist, an einen anderen Schichtaufbau laminiert ist, der ein elektrisch isolierendes zweites Substrat (6) und eine zweite elektrisch leitende Schicht, insbesondere eine Kupferfolie (7), die auf der ersten Seite des zweiten Substrats (6) angeordnet ist, umfaßt, wobei diese erste Seite von dem ersten Schichtaufbau abgekehrt ist, daß Fenster (8) oder Durchlöcher durch die Dicke des zweiten Schichtaufbaus angeordnet sind, um eine Anbringung von Komponenten (12) an dem leitenden Muster der ersten Schichtstruktur innerhalb der Fenster (8) oder Durchlöcher zu ermöglichen, und daß eine andere dritte leitende Schicht (4, 10), insbesondere eine Metallschicht, angeordnet ist, um die Kanten und Randabschnitte der zwei Schichtaufbauten zu bedecken, um die Masseleiter (3) des leitenden Musters und die leitende Schicht (7) des zweiten Schichtaufbaus elektrisch zu verbinden.<!-- EPO <DP n="19"> --></claim-text></claim>
<claim id="c-de-01-0002" num="0002">
<claim-text>Schaltungsplatine nach Anspruch 1, <b>dadurch gekennzeichnet, daß</b> die Fenster (8) oder Durchlöcher in dem zweiten Schichtaufbau in das Substrat (6) des zweiten Schichtaufbaus geschnitten sind und von der zweiten leitenden Schicht (7) weggeätzt sind.</claim-text></claim>
<claim id="c-de-01-0003" num="0003">
<claim-text>Schaltungsplatine nach einem der Ansprüche i-2, <b>dadurch gekennzeichnet, daß</b> die dritte leitende Schicht (4, 10) eine vierte leitende Schicht, insbesondere eine Kupferfolie (4), die nur auf die zweite Seite des ersten Schichtaufbaus angebracht ist, und eine fünfte leitende Schicht, die wenigstens die Kanten der Schaltungsplatine bedeckt, umfaßt.</claim-text></claim>
<claim id="c-de-01-0004" num="0004">
<claim-text>Schaltungsplatine nach einem der Ansprüche 1-3, <b>dadurch gekennzeichnet, daß</b> leitende Kappen (14, 26), insbesondere Metallkappen, an der zweiten leitenden Schicht (7) des zweiten Schichtaufbaus gelötet oder geklemmt sind, um die Fenster (8) abzudecken.</claim-text></claim>
<claim id="c-de-01-0005" num="0005">
<claim-text>Schaltungsplatine nach einem der Ansprüche 1-4, <b>dadurch gekennzeichnet, daß</b> die Masseleiter (3) des leitenden Musters des ersten Schichtaufbaus Abschnitte umfassen, insbesondere Kontaktanzapfungen (5), die über die Kante des Substrats (1) des ersten Schichtaufbaus hinaus vorstehen, um die dritte leitende Schicht (4, 10) zu kontaktieren, wobei die andere leitende Schicht und die Masseleiter (3) des leitenden Musters verbunden werden.</claim-text></claim>
<claim id="c-de-01-0006" num="0006">
<claim-text>Schaltungsplatine nach einem der Ansprüche 1-5, <b>dadurch gekennzeichnet, daß</b> die zweite leitende Schicht (7) des zweiten Schichtaufbaus (6) über die Kante des Substrats des zweiten Schichtaufbaus hinaus vorsteht, um die<!-- EPO <DP n="20"> --> dritte leitende Schicht (4, 10) zu kontaktieren, wobei die andere leitende Schicht und die Masseleiter (3) des leitenden Musters verbunden werden.</claim-text></claim>
<claim id="c-de-01-0007" num="0007">
<claim-text>Schaltungsplatine nach einem der Ansprüche 1-6, <b>dadurch gekennzeichnet, daß</b> das zweite Substrat (6) geringfügig größer als das erste Substrat (1) ist und daß die ersten und zweiten Substrate im Bezug zu einander in solcher Weise angeordnet sind, daß sich ein Rand des zweiten Substrats (6) über die Kante des ersten Substrats (1) hinaus entlang der Kanten der Schaltungsplatine erstreckt.</claim-text></claim>
<claim id="c-de-01-0008" num="0008">
<claim-text>Schaltungsplatine nach Anspruch 7, <b>dadurch gekennzeichnet, daß</b> der Rand eine Breite von im wesentlichen der gleichen Größe wie die Dicke der Substrate oder größer aufweist.</claim-text></claim>
<claim id="c-de-01-0009" num="0009">
<claim-text>Schaltungsplatine nach einem der Ansprüche 1-8, <b>gekennzeichnet durch</b> Fenster (20) oder Durchlöcher in dem ersten Substrat, wobei Bereiche oder Gebiete (18) der ersten leitenden Schicht auf der Oberseite dieser Fenster (20) oder Durchlöcher zurückgelassen sind, wobei die dritte leitende Schicht (4, 10) angeordnet ist, um die Kanten der leitenden Schichten innerhalb der Fenster (20) oder Durchlöcher und die Bereiche oder Gebiete (18) zu verbinden, um Massebereiche innerhalb des leitenden Musters in der ersten leitenden Schicht zu bilden.</claim-text></claim>
<claim id="c-de-01-0010" num="0010">
<claim-text>Schaltungsplatine nach Anspruch 3, <b>gekennzeichnet durch</b> Fenster (20) oder Durchlöcher in dem ersten Substrat, die auch durch die vierte leitende Schicht (4) gehen, wobei Bereiche oder Gebiete (18) der ersten leitenden<!-- EPO <DP n="21"> --> Schicht auf der Oberseite der Fenster (20) oder Durchlöcher zurückgelassen werden, wobei die dritte leitende Schicht (4, 10), insbesondere die fünfte leitende Schicht (10) angeordnet ist, um die Kanten der leitenden Schichten in den Fenstern (20) oder Durchlöchern und die Bereiche oder Gebiete (18) elektrisch zu verbinden, um Massebereiche innerhalb des Leitermusters in der ersten leitenden Schicht zu bilden.</claim-text></claim>
<claim id="c-de-01-0011" num="0011">
<claim-text>Schaltungsplatine nach einem der Ansprüche 1-10 mit bandförmigen oder streifenförmigen Leitern (40), die einen Teil der Schaltungsplatine mit einem anderen Teil davon verbinden, <b>dadurch gekennzeichnet, daß</b> Fenster (45) so gebildet sind, daß sie sich benachbart zu den bandförmigen oder streifenförmigen Leitern (40) durch den ersten Schichtaufbau und durch das Substrat (6) des zweiten Schichtaufbaus befinden, und daß sich die zweite leitende Schicht (7) über diese Fenster (45) erstreckt.</claim-text></claim>
<claim id="c-de-01-0012" num="0012">
<claim-text>Schaltungsplatine nach Anspruch 11, <b>dadurch gekennzeichnet, daß</b> über eine betrachtete Länge der bandförmigen oder streifenförmigen Leiter (40) eine Kante entweder von der Schaltungsplatine oder von den Fenstern (45) durch den ersten Schichtaufbau und durch das Substrat (6) des zweiten Schichtaufbaus auf beiden Seiten dieser Länge gebildet ist, wobei der Abstand von der Kante des Leiters (40) zu der Kante der Schaltungsplatine oder der Fenster (45) im wesentlichen konstant und gleich zu einander über diese betrachtete Länge ist.<!-- EPO <DP n="22"> --></claim-text></claim>
<claim id="c-de-01-0013" num="0013">
<claim-text>Schaltungsplatine nach einem der Ansprüche 1-12, <b>dadurch gekennzeichnet, daß</b> die Substrate (1, 6) aus Glasfaserverstärktem Plastik gebildet sind.</claim-text></claim>
<claim id="c-de-01-0014" num="0014">
<claim-text>Verfahren zum Herstellen einer Schaltungsplatine mit einem elektrisch leitenden Muster und elektrisch abgeschirmten Bereichen, <b>dadurch gekennzeichnet,</b>
<claim-text>- <b>daß</b> einem ersten elektrisch leitenden Substrat (1) eine gewünschte äußere Kontur oder ein Profil gegeben wird;</claim-text>
<claim-text>- <b>daß</b> eine erste elektrisch leitende Schicht, umfassend ein Leitermuster einschließlich Signalleitern (2) und Masseleitern (3), auf einer ersten Seite des ersten Substrats (1) erzeugt wird;</claim-text>
<claim-text>- <b>daß</b> einem zweiten elektrisch isolierenden Substrat (6) eine gewünschte äußere Kontur oder ein Profil gegeben wird und Fenster (8) oder Durchlöcher durch die Dicke des Substrats (6) erzeugt werden;</claim-text>
<claim-text>- <b>daß</b> eine zweite elektrische leitende Schicht (7) auf einer ersten Seite des zweiten Substrats (6) erzeugt wird;</claim-text>
<claim-text>- wonach Fenster in der zweiten leitenden Schicht (7) entsprechend zu den Fenstern (8) oder Durchlöchern in dem zweiten Substrat (6) erzeugt werden;</claim-text>
<claim-text>- wonach der zweite Schichtaufbau, der in dieser Weise aus dem zweiten Substrat (6) und der zweiten leitenden Schicht (7) gebildet ist, auf die<!-- EPO <DP n="23"> --> Oberseite des ersten Schichtaufbaus in solcher Weise plaziert wird, daß die zweite leitende Schicht (7) des zweiten Schichtaufbaus von dem ersten Schichtaufbau abgekehrt ist und die erste leitende Schicht (11) mit dem leitenden Muster des ersten Schichtaufbaus an der anderen zweiten Seite des zweiten Schichtaufbaus anliegt und die zwei Schichtaufbauten an einander angebracht werden;</claim-text>
<claim-text>- <b>daß</b> eine dritte elektrisch leitende Schicht (4, 10) auf diejenige zweite Seite des ersten Schichtaufbaus, die von dem zweiten Schichtaufbau abgekehrt ist, und die Kanten oder Randabschnitte der zwei Schichtaufbauten angebracht wird, um die Masseleiter (3) des leitenden Musters auf dem ersten Schichtaufbau und die zweite leitende Schicht (7) auf dem zweiten Substrat elektrisch zu verbinden;</claim-text>
<claim-text>- wonach Komponenten (12) in den Fenstern (8) oder Durchlöchern in dem zweiten Schichtaufbau an dem Schaltungsmuster des ersten Schichtaufbaus angebracht werden.</claim-text></claim-text></claim>
<claim id="c-de-01-0015" num="0015">
<claim-text>Verfahren nach Anspruch 14, <b>dadurch gekennzeichnet, daß</b> das erste isolierende Substrat (1) auf einer seiner Seiten mit einer vierten elektrisch leitenden Schicht (4) überzogen wird, bevor es mit der gewünschten Kontur oder dem Profil versehen wird.</claim-text></claim>
<claim id="c-de-01-0016" num="0016">
<claim-text>Verfahren nach Anspruch 15, <b>dadurch gekennzeichnet, daß</b> die dritte leitende Schicht (4, 10) eine fünfte elektrisch leitende Schicht (10) umfaßt, die auf<!-- EPO <DP n="24"> --> wenigstens die Randabschnitte derjenigen zweiten Seite des ersten Schichtaufbaus angebracht ist, die von dem zweiten Schichtaufbau abgekehrt ist und somit die vierte leitende Schicht (4) aufweist.</claim-text></claim>
<claim id="c-de-01-0017" num="0017">
<claim-text>Verfahren nach einem der Ansprüche 15-16, <b>dadurch gekennzeichnet, daß</b> Abschnitte der vierten leitenden Schicht (4) auf der Seite, die der Seite mit dem leitenden Muster des ersten Schichtaufbaus gegenüberliegt, weggeätzt werden und von irgendeiner elektrisch leitenden Beschichtung nicht überzogen sind, um einen Zugang zu dem leitenden Muster durch den ersten Schichtaufbau zu ermöglichen.</claim-text></claim>
<claim id="c-de-01-0018" num="0018">
<claim-text>Verfahren nach einem der Ansprüche 14-17, <b>dadurch gekennzeichnet, daß</b> die erste leitende Schicht (11) geätzt wird, um das leitende Muster einschließlich der Signalleiter (2) und Masseleiter (3) zu erzeugen.</claim-text></claim>
<claim id="c-de-01-0019" num="0019">
<claim-text>Verfahren nach einem der Ansprüche 14-18, <b>dadurch gekennzeichnet, daß</b> die Fenster in der zweiten leitenden Schicht (7) geätzt werden.</claim-text></claim>
<claim id="c-de-01-0020" num="0020">
<claim-text>Verfahren nach einem der Ansprüche 14-19, <b>dadurch gekennzeichnet, daß</b> die zwei Schichtaufbauten anhaftend an einander gebondet sind.</claim-text></claim>
<claim id="c-de-01-0021" num="0021">
<claim-text>Verfahren nach einem der Ansprüche 14-20, <b>dadurch gekennzeichnet, daß</b> auf der Oberseite der Fenster (8) oder Durchlöcher Metallkappen (14, 26) an die zweite leitende Schicht (7) des zweiten Substrats (6) angelötet oder geklemmt sind.<!-- EPO <DP n="25"> --></claim-text></claim>
<claim id="c-de-01-0022" num="0022">
<claim-text>Verfahren nach einem der Ansprüche 14-21, <b>dadurch gekennzeichnet, daß</b> die dritte leitende Schicht (4, 7) wenigstens teilweise mittels eines thermischen Sprühens eines niedrig-schmelzenden Metalls, insbesondere von Zinn oder einer Legierung davon, angebracht wird.</claim-text></claim>
<claim id="c-de-01-0023" num="0023">
<claim-text>Verfahren nach einem der Ansprüche 14-22, <b>dadurch gekennzeichnet, daß</b> Fenster (20) oder Durchlöcher auch in dem ersten Substrat (1) gebildet werden, wobei diese Fenster oder Durchlöcher davor geschützt werden, irgendeine leitende Schicht auf der anderen zweite Seite des ersten Schichtaufbaus zu erhalten, um einen Zugang zu dem leitenden Muster durch den ersten Schichtaufbau zu ermöglichen.</claim-text></claim>
<claim id="c-de-01-0024" num="0024">
<claim-text>Verfahren nach Anspruch 23, <b>dadurch gekennzeichnet, daß</b> Abschnitte, die den Fenstern oder Durchlöchern in dem ersten Substrat entsprechen, einer vierten elektrisch leitenden Schicht (4) auf der Seite, die der Seite mit dem leitenden Muster des ersten Schichtaufbaus gegenüberliegt, weggeätzt und gegenüber irgendeiner elektrisch leitenden Beschichtung maskiert werden.</claim-text></claim>
<claim id="c-de-01-0025" num="0025">
<claim-text>Verfahren nach einem der Ansprüche 14-24, <b>dadurch gekennzeichnet, daß</b> andere Schaltungsmusterplatinen an den ersten Schichtaufbau laminiert werden und daß Löcher gebohrt und mit einer elektrisch leitenden Schicht beschichtet werden, um Leiter der anderen Schaltungsmusterplatinen mit dem Schaltungsmuster auf dem ersten Schichtaufbau zu verbinden.<!-- EPO <DP n="26"> --></claim-text></claim>
<claim id="c-de-01-0026" num="0026">
<claim-text>Verfahren zur Herstellung von Schaltungsplatinen mit einem elektrisch leitenden Muster und abgeschirmten Bereichen, <b>dadurch gekennzeichnet,</b>
<claim-text>- <b>daß</b> ein erstes elektrisch isolierendes Substrat (1), welches auf einer seiner Seiten mit einer elektrisch leitenden Schicht (4), insbesondere einer Kupferfolie, überzogen sein kann, geschnitten wird, um dem ersten Substrat (1) zusammen mit der möglichen leitenden Schicht (4) eine gewünschte äußere Kontur oder ein Profil zu geben,</claim-text>
<claim-text>- wonach eine andere erste elektrisch leitende Schicht (11), insbesondere eine Kupferfolie, an der anderen ersten Seite des ersten Substrats (1) angebracht, insbesondere daran laminiert, wird, um die erste Seite vollständig zu bedecken; und</claim-text>
<claim-text>- die erste leitende Schicht (11) geätzt wird, um ein leitendes Muster umfassend Signalleiter (2) und Masseleiter (3), der ersten Seite des ersten Substrats (19) zu erzeugen; und</claim-text>
<claim-text>- <b>daß</b> ein zweites elektrisch isolierendes Substrat (6) geschnitten wird, um es mit einer gewünschten äußeren Kontur oder mit einem Profil und Fenstern (8) oder Durchlöchern durch die Dicke dieses Substrats (6) zu versehen, und daß es mit einer zweiten elektrisch leitenden Schicht (7), insbesondere einer Kupferfolie, auf einer seiner Seiten, der ersten davon, überzogen, insbesondere daran laminiert, wird;<!-- EPO <DP n="27"> --></claim-text>
<claim-text>- wonach Fenster in die zweite leitende Schicht (7) entsprechend zu den Fenstern (8) oder Durchlöchern, die in das zweite Substrat (6) geschnitten sind, geätzt werden;</claim-text>
<claim-text>- wonach der zweite Schichtaufbau, der in dieser Weise aus dem zweiten Substrat (6) und der zweiten leitenden Schicht (7) gebildet ist, auf der Oberseite des ersten Schichtaufbaus in solcher Weise plaziert wird, daß die zweite leitende Schicht (7) des zweiten Schichtaufbaus von dem ersten Schichtaufbau abgekehrt ist und die erste leitende Schicht (11) mit dem leitenden Muster des ersten Schichtaufbaus an der anderen zweiten Seite des zweiten Schichtaufbaus anliegt und die zwei Schichtaufbauten anhaftend an einander gebondet werden; und</claim-text>
<claim-text>- <b>daß</b> eine elektrisch leitende Schicht (10), insbesondere eine Metallschicht, angebracht wird auf wenigstens die Randabschnitte derjenigen zweiten Seite des ersten Schichtaufbaus, die von dem zweiten Schichtaufbau abgekehrt ist und somit eine leitende Schicht (4) aufweisen kann, und die Kanten oder Randabschnitte der zwei Schichtaufbauten, um die Seite des ersten Schichtaufbaus, Masseleiter (3) des leitenden Musters auf dem ersten Schichtaufbau und die dritte leitende Schicht (7) auf dem zweiten Substrat elektrisch zu verbinden,</claim-text>
<claim-text>- wonach Komponenten (12) in den Fenstern (8) oder Durchlöchern in dem zweiten Schichtaufbau an dem<!-- EPO <DP n="28"> --> Schaltungsmuster des ersten Schichtaufbaus angebracht werden.</claim-text></claim-text></claim>
</claims><!-- EPO <DP n="29"> -->
<claims id="claims03" lang="fr">
<claim id="c-fr-01-0001" num="0001">
<claim-text>Plaquette à circuits ayant un motif électriquement conducteur et des régions électriquement blindées, caractérisée en ce qu'un premier stratifié comprenant un premier substrat électriquement isolant (1) ayant une première couche conductrice, la première couche comprenant un motif électriquement conducteur de conducteurs (2) de signaux et de conducteurs (3) de masse et étant placée sur un premier côté du premier stratifié, est appliqué en stratification, par le premier côté ayant le motif conducteur, sur un autre stratifié comportant un second substrat électriquement isolant (6) et une seconde couche électriquement conductrice, en particulier une mince feuille de cuivre (7) disposée sur le premier côté du second substrat (6), ce premier côté étant tourné à l'écart du premier stratifié, en ce que des fenêtres (8) ou des trous traversants sont ménagés à travers l'épaisseur du second stratifié pour permettre le montage de composants (12) sur le motif conducteur du premier stratifié à l'intérieur des fenêtres (8) ou des trous traversants, et en ce qu'une autre, troisième, couche conductrice (4, 10), en particulier une couche métallique, est disposée de façon à recouvrir les bords ou parties marginales des deux stratifiés pour connecter électriquement les conducteurs de masse (3) du motif conducteur et la couche conductrice (7) du second stratifié.</claim-text></claim>
<claim id="c-fr-01-0002" num="0002">
<claim-text>Plaquette à circuits selon la revendication 1, caractérisée en ce que les fenêtres (8) ou les trous traversants du second stratifié sont découpées dans le substrat (6) du second stratifié et sont enlevées par attaque chimique de la seconde couche conductrice (7).</claim-text></claim>
<claim id="c-fr-01-0003" num="0003">
<claim-text>Plaquette à circuits selon l'une des revendications 1 et 2, caractérisée en ce que la troisième couche conductrice (4, 10) comprend une quatrième couche conductrice, en particulier une mince feuille de cuivre (4), appliquée seulement sur le second côté du premier stratifié, et une<!-- EPO <DP n="30"> --> cinquième couche conductrice recouvrant au moins les bords de la plaquette à circuits.</claim-text></claim>
<claim id="c-fr-01-0004" num="0004">
<claim-text>Plaquette à circuits selon l'une des revendications 1 à 3, caractérisée en ce que des coiffes conductrices (14, 26), en particulier des coiffes métalliques, sont soudées ou bridées sur la deuxième couche conductrice (7) du second stratifié pour recouvrir les fenêtres (8).</claim-text></claim>
<claim id="c-fr-01-0005" num="0005">
<claim-text>Plaquette à circuits selon l'une des revendications 1 à 4, caractérisée en ce que les conducteurs de masse (3) du motif conducteur du premier stratifié comportent des parties, en particulier des pattes (5) de contact, faisant saillie au-delà du bord du substrat (1) du premier stratifié pour entrer en contact avec la troisième couche conductrice (4, 10) connectant l'autre couche conductrice et les conducteurs de masse (3) du motif conducteur.</claim-text></claim>
<claim id="c-fr-01-0006" num="0006">
<claim-text>Plaquette à circuits selon l'une des revendications 1 à 5, caractérisée en ce que la deuxième couche conductrice (7) du second stratifié (6) fait saillie au-delà du bord du substrat du second stratifié pour entrer en contact avec la troisième couche conductrice (4, 10) connectant l'autre couche conductrice et les conducteurs de masse (3) du motif conducteur.</claim-text></claim>
<claim id="c-fr-01-0007" num="0007">
<claim-text>Plaquette à circuits selon l'une des revendications 1 à 6, caractérisée en ce que le second substrat (6) est légèrement plus grand que le premier substrat (1) et en ce que les premier et second substrats sont disposés l'un par rapport à l'autre de façon qu'une marge du second substrat (6) s'étende au-delà du bord du premier substrat (1) le long des bords de la plaquette à circuits.</claim-text></claim>
<claim id="c-fr-01-0008" num="0008">
<claim-text>Plaquette à circuits selon la revendication 7, caractérisée en ce que la marge présente une largeur essentiellement de même dimension, ou plus, que l'épaisseur des substrats.</claim-text></claim>
<claim id="c-fr-01-0009" num="0009">
<claim-text>Plaquette à circuits selon l'une des revendications 1 à 8, caractérisée par des fenêtres (20) ou des<!-- EPO <DP n="31"> --> trous traversants dans le premier substrat, des régions ou zones (18) de la première couche conductrice étant laissées sur le dessus de ces fenêtres (20) ou trous traversants, la troisième couche conductrice (4, 10) étant disposée de manière à connecter électriquement les bords des couches conductrices à l'intérieur des fenêtres (20) ou des trous traversants et les régions ou zones (18) pour former des zones mises à la masse à l'intérieur du motif conducteur dans la première couche conductrice.</claim-text></claim>
<claim id="c-fr-01-0010" num="0010">
<claim-text>Plaquette à circuits selon la revendication 3, caractérisée par des fenêtres (20) ou des trous traversants dans le premier substrat, passant aussi à travers la quatrième couche conductrice (4), des régions ou zones (18) de la première couche conductrice étant laissées sur le dessus des fenêtres (20) ou des trous traversants, et la troisième couche conductrice (4, 10), en particulier la cinquième couche conductrice (10), étant disposée de façon à connecter électriquement les bords des couches conductrices à l'intérieur des fenêtres (20) ou des trous traversants et les régions ou zones (18) pour former des zones mises à la masse à l'intérieur du motif conducteur dans la première couche conductrice.</claim-text></claim>
<claim id="c-fr-01-0011" num="0011">
<claim-text>Plaquette à circuits selon l'une des revendications 1 à 10, ayant des conducteurs (40) en forme de bande ou en forme de ruban connectant une partie de la plaquette à circuits à une autre partie de celle-ci, caractérisée en ce que des fenêtres (45) sont réalisées de façon à être adjacentes au conducteur (40) en forme de bande ou en forme de ruban, à travers le premier stratifié et à travers le substrat (6) du second stratifié, et en ce que la deuxième couche conductrice (7) s'étend au-dessus de ces fenêtres (45).</claim-text></claim>
<claim id="c-fr-01-0012" num="0012">
<claim-text>Plaquette à circuits selon la revendication 11, caractérisée en ce qu'il y a, au-dessus d'une longueur considérée des conducteurs (40) en forme de bande ou en forme<!-- EPO <DP n="32"> --> de ruban, un bord soit de la plaquette à circuits, soit des fenêtres (45) réalisées à travers le premier stratifié et à travers le substrat (6) du second stratifié sur les deux côtés de cette longueur, la distance allant du bord du conducteur (40) jusqu'au bord de la plaquette à circuits ou des fenêtres (45) étant sensiblement constante et la même sur cette longueur considérée.</claim-text></claim>
<claim id="c-fr-01-0013" num="0013">
<claim-text>Plaquette à circuits selon l'une des revendications 1 à 12, caractérisée en ce que les substrats (1, 6) sont réalisés en matière plastique armée de fibres de verre.</claim-text></claim>
<claim id="c-fr-01-0014" num="0014">
<claim-text>Procédé de fabrication d'une plaquette à circuits ayant un motif électriquement conducteur et des régions électriquement blindées, caractérisé en ce que
<claim-text>on donne à un premier substrat électriquement isolant (1) un contour ou profil extérieur souhaité,</claim-text>
<claim-text>on produit, sur un premier côté du premier substrat (1), une première couche électriquement conductrice comprenant un motif conducteur qui comporte des conducteurs de signaux (2) et des conducteurs de masse (3),</claim-text>
<claim-text>on donne un contour ou profil extérieur souhaité à un second substrat électriquement isolant (6) et on produit des fenêtres (8) ou des trous traversants à travers l'épaisseur du substrat (6),</claim-text>
<claim-text>on produit une deuxième couche électriquement conductrice (7) sur un premier côté du second substrat (6),</claim-text>
<claim-text>on produit ensuite dans la deuxième couche conductrice (7) des fenêtres correspondant aux fenêtres (8) ou aux trous traversants du second substrat (6),</claim-text>
<claim-text>on place ensuite sur le dessus du premier stratifié le second stratifié formé de cette manière à partir du second substrat (6) et de la deuxième couche conductrice (7), de façon que la deuxième couche conductrice (7) du second stratifié soit tournée à l'écart du premier stratifié et que la première couche conductrice (11) ayant le motif conducteur du premier stratifié soit appliquée contre<!-- EPO <DP n="33"> --> l'autre, second côté du second stratifié et que les deux stratifiés soient reliés l'un à l'autre, et</claim-text>
<claim-text>on applique une troisième couche électriquement conductrice (4, 10) sur ce second côté du premier stratifié, qui est tourné à l'écart du second stratifié, et sur les bords ou les parties marginales des deux stratifiés afin de connecter électriquement les conducteurs de masse (3) du motif conducteur sur le premier stratifié et la deuxième couche conductrice (7) sur le second substrat,</claim-text>
<claim-text>des composants (12) sont ensuite montés dans les fenêtres (8) ou dans les trous traversants du second stratifié sur le motif de circuits du premier stratifié.</claim-text></claim-text></claim>
<claim id="c-fr-01-0015" num="0015">
<claim-text>Procédé selon la revendication 14, caractérisé en ce que l'un des côtés du premier substrat isolant (1) est revêtu d'une quatrième couche électriquement conductrice (4) avant que le contour ou profil souhaité ne soit donné au substrat.</claim-text></claim>
<claim id="c-fr-01-0016" num="0016">
<claim-text>Procédé selon la revendication 15, caractérisé en ce que la troisième couche conductrice (4, 10) comprend une cinquième couche électriquement conductrice (10) appliquée au moins sur les parties marginales du second côté du premier substrat, qui est tourné à l'écart du second stratifié, et qui comporte donc la quatrième couche conductrice (4).</claim-text></claim>
<claim id="c-fr-01-0017" num="0017">
<claim-text>Procédé selon l'une des revendications 15 et 16, caractérisé en ce que des parties de la quatrième couche conductrice (4) situées sur le côté opposé au côté ayant le motif conducteur du premier stratifié sont enlevées par attaque chimique et ne sont recouvertes d'aucun revêtement électriquement conducteur afin de permettre un accès au motif conducteur à travers le premier stratifié.</claim-text></claim>
<claim id="c-fr-01-0018" num="0018">
<claim-text>Procédé selon l'une des revendications 14 à 17, caractérisé en ce que la première couche conductrice (11) est soumise à une attaque chimique pour produire le motif conducteur comprenant les conducteurs (2) de signaux et les<!-- EPO <DP n="34"> --> conducteurs (3) de masse.</claim-text></claim>
<claim id="c-fr-01-0019" num="0019">
<claim-text>Procédé selon l'une des revendications 14 à 18, caractérisé en ce que les fenêtres sont réalisées par attaque chimique dans la deuxième couche conductrice (17).</claim-text></claim>
<claim id="c-fr-01-0020" num="0020">
<claim-text>Procédé selon l'une des revendications 14 à 19, caractérisé en ce que les deux stratifiés sont liés l'un à l'autre par un adhésif.</claim-text></claim>
<claim id="c-fr-01-0021" num="0021">
<claim-text>Procédé selon l'une des revendications 14 à 20, caractérisé en ce que des coiffes métalliques (14, 26) sont soudées ou bridées à la deuxième couche conductrice (7) du second stratifié (6), sur le dessus des fenêtres (8) ou des trous traversants.</claim-text></claim>
<claim id="c-fr-01-0022" num="0022">
<claim-text>Procédé selon l'une des revendications 14 à 21, caractérisé en ce que la troisième couche conductrice (4, 10) est appliquée au moins partiellement par pulvérisation thermique d'un métal à bas point de fusion, en particulier de l'étain ou un alliage d'étain.</claim-text></claim>
<claim id="c-fr-01-0023" num="0023">
<claim-text>Procédé selon l'une des revendications 14 à 22, caractérisé en ce que des fenêtres (20) ou des trous traversants sont également réalisés dans le premier substrat (1), où ces fenêtres ou trous traversants sont protégés de façon à ne recevoir aucune couche conductrice sur l'autre, second, côté du premier stratifié, pour permettre un accès au motif conducteur à travers le premier stratifié.</claim-text></claim>
<claim id="c-fr-01-0024" num="0024">
<claim-text>Procédé selon la revendication 23, caractérisé en ce que des parties, correspondant aux fenêtres ou aux trous traversants du premier substrat, d'une quatrième couche électriquement conductrice (4), sur le côté opposé au côté ayant le motif conducteur du premier stratifié, sont enlevées par attaque chimique et masquées à l'encontre de tout revêtement électriquement conducteur.</claim-text></claim>
<claim id="c-fr-01-0025" num="0025">
<claim-text>Procédé selon l'une des revendications 14 à 24, caractérisé en ce que d'autres plaquettes ayant des motifs de circuits sont appliquées par stratification sur le premier stratifié et des trous sont percés et revêtus d'une<!-- EPO <DP n="35"> --> couche électriquement conductrice pour connecter les conducteurs des autres plaquettes à motifs de circuits au motif de circuit se trouvant sur le premier stratifié.</claim-text></claim>
<claim id="c-fr-01-0026" num="0026">
<claim-text>Procédé de fabrication de plaquette à circuits ayant un motif électriquement conducteur et des régions blindées, caractérisé en ce que
<claim-text>un premier substrat électriquement isolant (1), qui peut être revêtu, sur l'un de ses côtés, d'une couche électriquement conductrice (4), en particulier une mince feuille de cuivre, est découpé pour donner au premier substrat (1), en même temps que la couche conductrice possible (4), un contour ou profil extérieur souhaité,</claim-text>
<claim-text>après quoi une autre première couche électriquement conductrice (11), en particulier une mince feuille de cuivre, est appliquée, et en particulier stratifiée sur, l'autre, premier, côté du premier substrat (1) pour recouvrir entièrement le premier côté, et</claim-text>
<claim-text>la première couche conductrice (11) est soumise à une attaque chimique pour produire un motif conducteur comprenant des conducteurs (2) de signaux et des conducteurs (3) de masse sur le premier côté du premier substrat (1), et</claim-text>
<claim-text>un second substrat électriquement isolant (6) est découpé afin de lui donner un contour ou profil extérieur souhaité et des fenêtres (8) ou des trous traversants à travers l'épaisseur de ce substrat (6), et celui-ci est revêtu d'une seconde couche électriquement conductrice (7), en particulier par stratification avec elle, laquelle est en particulier une mince feuille de cuivre, sur l'un de ses côtés, le premier de ceux-ci,</claim-text>
<claim-text>après quoi des fenêtres sont réalisées par attaque chimique dans la deuxième couche conductrice (7) de façon à correspondre aux fenêtres (8) ou aux trous traversants découpés dans le second substrat (6),</claim-text>
<claim-text>après quoi le second stratifié formé de cette manière à partir du second substrat (6) et de la deuxième<!-- EPO <DP n="36"> --> couche conductrice (7) est placé sur le dessus du premier stratifié de façon que la deuxième couche conductrice (7) du second stratifié soit tournée à l'écart du premier stratifié et que la première couche conductrice (11), ayant le motif conducteur du premier stratifié, soit appliquée contre l'autre, second, côté du second stratifié et que les deux stratifiés soient liés l'un à l'autre par un adhésif, et</claim-text>
<claim-text>une couche électriquement conductrice (10), en particulier une couche métallique, est appliquée au moins sur les parties marginales du second côté du premier stratifié, qui est tourné à l'écart du second stratifié, et qui peut donc avoir une couche conductrice (4), et sur les bords ou parties marginales des deux stratifiés pour connecter électriquement le côté du premier stratifié, les conducteurs de masse (3) du motif conducteur sur le premier stratifié et la troisième couche conductrice (7) sur le second substrat,</claim-text>
<claim-text>après quoi des composants (12) sont montés dans les fenêtres (8) ou les trous traversants dans le second stratifié, sur le motif de circuits du premier stratifié.</claim-text></claim-text></claim>
</claims><!-- EPO <DP n="37"> -->
<drawings id="draw" lang="en">
<figure id="f0001" num=""><img id="if0001" file="imgf0001.tif" wi="166" he="239" img-content="drawing" img-format="tif"/></figure><!-- EPO <DP n="38"> -->
<figure id="f0002" num=""><img id="if0002" file="imgf0002.tif" wi="161" he="237" img-content="drawing" img-format="tif"/></figure><!-- EPO <DP n="39"> -->
<figure id="f0003" num=""><img id="if0003" file="imgf0003.tif" wi="107" he="218" img-content="drawing" img-format="tif"/></figure><!-- EPO <DP n="40"> -->
<figure id="f0004" num=""><img id="if0004" file="imgf0004.tif" wi="153" he="216" img-content="drawing" img-format="tif"/></figure>
</drawings>
</ep-patent-document>
