(57) A display module drive circuit has a gate driver and a source driver. The source
driver has a shift register (1), a sampling memory (2), a hold memory (3), a timing
signal generating circuit (4), a voltage control circuit (5), and an output voltage
generating circuit (6) having a capacitor and a switch. The timing signal generating
circuit (4) generates timing signals (T₀-T₇) having different pulse widths in each
of horizontal periods. The number of the timing signals (T₀-T₇) depends on the number
of density levels of an image to be displayed. Upon receipt of digital video signals
(HnD₀, HnD₁, HnD₂) and the timing signals (T₀-T₇), the voltage control circuit (5)
selects one of the timing signals (T₀-T₇) based on the contents of the video signals
(HnD₀, HnD₁, and HnD₂) in each horizontal period and outputs a control signal (CON1,
CON2) at a specified level for a period corresponding to the pulse width of the selected
timing signal. The capacitor of the output voltage generating circuit (6) is charged
with an external power voltage while the control signal (CON1, CON2) is being received
by the switch, so that a drive voltage is generated. The external power voltage is
supplied from an external power source offering an electrical potential which becomes
higher with time.
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