(19)
(11) EP 0 551 910 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
30.08.1995 Bulletin 1995/35

(43) Date of publication A2:
21.07.1993 Bulletin 1993/29

(21) Application number: 93100556.5

(22) Date of filing: 15.01.1993
(51) International Patent Classification (IPC)5: H03F 1/30, G09G 3/36, G11C 27/02
(84) Designated Contracting States:
DE GB

(30) Priority: 16.01.1992 JP 5858/92

(71) Applicant: KABUSHIKI KAISHA TOSHIBA
Kawasaki-shi, Kanagawa-ken 210 (JP)

(72) Inventor:
  • Minamizaki, Hironori
    Kawasaki-shi, Kanagawa-ken (JP)

(74) Representative: Lehn, Werner, Dipl.-Ing. et al
Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20
81904 München
81904 München (DE)


(56) References cited: : 
   
       


    (54) Offset detecting circuit and output circuit and integrated circuit including the output circuit


    (57) An offset detecting circuit (10) includes: a sample hold circuit (12) for holding a reference voltage Vref; and a buffer amplifier (13) having two pairs of input terminals. The reference voltage Vref is applied to at least one input terminal of one pair of the two input terminal pairs, and an output signal of the sample hold circuit (12) and an output signal VDout of the buffer amplifier (13) are applied to the other pair of the two input terminal pairs of the buffer amplifier (13), respectively. Further, an output circuit is composed of this offset detecting circuit (10) and a signal voltage outputting circuit (20) configured in the same way as the offset detecting circuit (10). The signal voltage outputting circuit (20) corrects the offset of a signal Vin inputted thereto on the basis of an offset voltage V between the reference voltage Vref and the output voltage VDout supplied from the offset voltage detecting circuit (10).
    The offset detecting circuit (10) and the signal voltage outputting circuits (20) can be integrated on the same substrate or on different substrates, separately as occasion demands.






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