Vertical and lateral isolation for a semiconductor device

(19)

(11)

EP 0 559 405 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	10.09.1997 Bulletin 1997/37

(43)	Date of publication A2:
	08.09.1993 Bulletin 1993/36

(21)	Application number: 93301518.2

(22)	Date of filing: 01.03.1993

(51)	International Patent Classification (IPC)⁵: H01L 21/76, H01L 21/20

(84)	Designated Contracting States:
	DE FR GB IT

(30)

Priority:

03.03.1992 US 845409

(71)	Applicant: MOTOROLA, INC.
	Schaumburg, IL 60196 (US)

(72)	Inventors:
	Cambou, Bertrand F. Mesa, Arizona 85202 (US) Hughes, Donald L. Mesa, Arizona 85213 (US)

(74)	Representative: Hudson, Peter David et al
	Motorola European Intellectual Property Midpoint Alencon Link Basingstoke, Hampshire RG21 7PL Basingstoke, Hampshire RG21 7PL (GB)

(54)	Vertical and lateral isolation for a semiconductor device

(57) A method is provided for making a power device (54) and a small signal device (52) on a bonded silicon substrate (41). A first silicon substrate (10) provided. A first surface (17) is etched to form a plurality of cavities (11) with a depth (13). A dielectric layer (14) is created on the first surface (17), wherein the dielectric layer (14) is created with a thickness less than or equal to the depth of the plurality of cavities. The dielectric layer (14) is patterned so that a plurality of islands (22) of dielectric remain in the cavities. A second silicon substrate (42) is provided. The first and the second silicon substrates (10, 42) are bonded together in such a manner that the islands (22) are buried. A predetermined portion of the first silicon substrate (10) is removed, thereby creating a surface that is suitable for semiconductor device fabrication.

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