(19)
(11) EP 0 591 672 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
24.08.1994 Bulletin 1994/34

(43) Date of publication A2:
13.04.1994 Bulletin 1994/15

(21) Application number: 93113642.8

(22) Date of filing: 26.08.1993
(51) International Patent Classification (IPC)5: H01L 21/82, H01L 21/84
(84) Designated Contracting States:
DE FR GB

(30) Priority: 05.10.1992 US 956224

(71) Applicant: MOTOROLA, INC.
Schaumburg, IL 60196 (US)

(72) Inventors:
  • Hwang, Bor-Yuan
    Tempe, Arizona 85284 (US)
  • Foerstner, Jürgen A.
    Mesa, Arizona 85203 (US)

(74) Representative: Hudson, Peter David et al
Motorola European Intellectual Property Midpoint Alencon Link
Basingstoke, Hampshire RG21 7PL
Basingstoke, Hampshire RG21 7PL (GB)


(56) References cited: : 
   
       


    (54) Method for fabricating bipolar junction and MOS transistors on SOI


    (57) An SOI wafer (10) is separated into a bipolar junction transistor area (18) and an MOS transistor area (19). A bipolar junction transistor having a collector region (25), and emitter region (44), an inactive base region (33), and an active base region (43) is formed on a thin film of semiconductor material (13) in the bipolar junction transistor area (18). A link between the inactive base region (33) and the active base region (43) is formed from a polysilicon spacer (42) along an edge or sidewall of emitter openings (39 or 40). Simultaneously with the formation of the bipolar junction transistor, MOS transistors are formed in the MOS transistor area (19). Electrically conductive contacts (56) in the bipolar junction transistor area (18) and the MOS transistor area (19) are formed from a silicide. Both complementary bipolar junction transistors and MOS transistors may be formed.






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