(19)
(11) EP 0 601 768 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
06.09.1995 Bulletin 1995/36

(43) Date of publication A2:
15.06.1994 Bulletin 1994/24

(21) Application number: 93309545.7

(22) Date of filing: 30.11.1993
(51) International Patent Classification (IPC)5: H04L 12/26
(84) Designated Contracting States:
DE FR GB

(30) Priority: 30.11.1992 JP 319572/92

(71) Applicant: NEC CORPORATION
Tokyo (JP)

(72) Inventor:
  • Ojima, Sawako
    Minato-ku, Tokyo (JP)

(74) Representative: Cozens, Paul Dennis et al
Mathys & Squire 100 Grays Inn Road
London WC1X 8AL
London WC1X 8AL (GB)


(56) References cited: : 
   
       


    (54) Bus monitor circuit for switching system and method of monitoring


    (57) In a switching system, a data bus which interconnects circuit modules, a switching network module and a control module for transporting packets between the interconnected modules. A bus interface (16) is connected to the data bus (13) for receiving a copy of every packet on the data bus. An error detector (18) determines whether the received packet contains an error, and produces an error detect signal and an error check result if the received packet is determined as having an error. In response to the error detect signal, the received packet, the error check result and time-of-day data are stored into a register (19) and transferred to one of the storage locations of a memory (20) to keep a list of error records. A maintenance station (22) reads stored error records from the memory for identifying the source of errors.






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