Dual gate JFET circuit to control threshold voltage

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EP 0 609 009 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	02.11.1994 Bulletin 1994/44

(43)	Date of publication A2:
	03.08.1994 Bulletin 1994/31

(21)	Application number: 94300383.0

(22)	Date of filing: 19.01.1994

(51)	International Patent Classification (IPC)⁵: G05F 1/56, G05F 3/24

(84)	Designated Contracting States:
	DE FR GB IT

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Priority:

28.01.1993 US 10380

(71)	Applicant: NATIONAL SEMICONDUCTOR CORPORATION
	Santa Clara, California 95052-8090 (US)

(72)	Inventor:
	Farrenkopf, Doug R. Santa Clara, California 95051 (US)

(74)	Representative: Horton, Andrew Robert Grant et al
	BOWLES HORTON Felden House Dower Mews High Street Berkhamsted Hertfordshire HP4 2BL Berkhamsted Hertfordshire HP4 2BL (GB)

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References cited: :

(54)	Dual gate JFET circuit to control threshold voltage

(57) A monolithic integrated circuit includes a plurality of dual gate junction field effect transistors. One is selected as a standard transistor and its current is passed through a first resistor. A reference current is passed through a second resistor. The two resistors are coupled to the inputs of an op-amp, the output of which is coupled to one gate of the standard transistor. The other gate of the standard transistor is supplied with a bias voltage selected to operate the transistor in the conducting mode. Thus, the standard transistor forms a negative feedback loop around the op-amp. As a result, the standard transistor will pass a current related to the reference current in a ratio determined by the ratio of the resistor values. The op-amp output can then be coupled to the other gates in all of the other transistors in the integrated circuit. Accordingly, all of the transistors will have their operating currents the same as that of the standard transistor at the same operating bias. This means that all of the transistors display the same effective threshold voltage.

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