(19)
(11) EP 0 614 152 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
31.01.1996 Bulletin 1996/05

(43) Date of publication A2:
07.09.1994 Bulletin 1994/36

(21) Application number: 94102226.1

(22) Date of filing: 14.02.1994
(51) International Patent Classification (IPC)5: G06F 15/60
(84) Designated Contracting States:
DE FR GB

(30) Priority: 05.03.1993 US 27016

(71) Applicant: International Business Machines Corporation
Armonk, N.Y. 10504 (US)

(72) Inventors:
  • Myers, John David
    Endwell, New York 13760 (US)
  • Rivero, Jose Luis
    Boca Raton, Florida 33498 (US)

(74) Representative: Schäfer, Wolfgang, Dipl.-Ing. 
IBM Deutschland Informationssysteme GmbH Patentwesen und Urheberrecht
D-70548 Stuttgart
D-70548 Stuttgart (DE)


(56) References cited: : 
   
       


    (54) System for optimal electronic debugging and verification employing scheduled cutover of alternative logic simulations


    (57) A system for determining the optimal circuit design simulator schedule for debugging a digital electronic circuit design. The system characterizes all available circuit design simulators in terms of several parameters reflecting simulator speed and the time required to discover, isolate and fix a design error (bug). A cutover point is established for any pair of available simulators on the basis of these parameters. One simulator is progressively more efficient than the other beyond this cutover point, which is the desired time for scheduling substitution of the more efficient simulator during the debugging process. The system also permits "what-if" evaluation of alternative debugging strategies in advance by creating alternative schedules in response to various characteristic parameters.






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