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(11) | EP 0 622 801 A2 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Hierarchical bitline memory architecture |
| (57) In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline
configuration is utilized such that a number of local bitlines are connected to a
master bitline through interface circuitry which connects a local bitline to the master
bitline. Local select signals, when set to the appropriate voltage level, couple a
local bitline to the master bitline. In addition to reducing the local bitline capacitance
that must be driven by memory cells, the hierarchical configuration may provide layout
area savings as well. Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines. |
[0001] The present invention relates generally to integrated circuits, including hierarchical bitline memory architecture and interface circuitry within the hierarchical bitline memory architecture which provides gain and/or isolation characteristics.
[0002] In recent years, high density memories such as SRAMs, DRAMs, EPROMs, and EEPROMs have dramatically increased the level of bitline capacitance which must be driven by memory cells in the memory array. As high speed memories have increased in density, efforts have been made to carefully partition the memory array to reduce the burden on the memory cell for driving large bitline capacitances. For example, memory arrays have gone to four times the number of columns as rows to reduce bitline capacitance. In addition, the rows are sometimes bisected by the sensing and column decode circuitry to further reduce bitline capacitance. In spite of the advances made in careful partitioning of the memory array, bitline capacitance can still be prohibitively large, having an adverse affect on device speed and signal integrity. As a result, better methods for reducing the bitline capacitance as seen by memory cells while using minimum layout area are needed and appropriate.
[0003] In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well.
[0004] Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines.
[0005] According to a preferred embodiment of the present invention there is provided a partitioned memory array, comprising a plurality of master bitlines, a plurality of local bitlines connected to a plurality of memory cells, a plurality of interface circuits, which connects each master bitline to at least two of the local bitlines, and a plurality of local select signals, each capable of selecting a corresponding local bitline to be coupled to its corresponding master bitline.
[0010] Preferably the n-channel transistor has a lower VT such that the voltage drop across it is minimized.
[0011] Preferably the well in which the n-channel transistor resides is pumped to a lower voltage which is less than a second supply voltage.
[0013] The interface circuitry may be comprised of a full CMOS transmission gate having an n-channel transistor and a p-channel transistor.
[0014] Preferably the gate of the n-channel transistor is connected to a local select signal and the gate of the p-channel transistor is connected to the complement of the local select signal.
[0015] Each local bitline may be connected to a loading element such that it is tied to a predetermined voltage level.
[0020] The memory array may be formed using a first metal layer, a second metal layer, and a third metal layer.
[0023] A metal layer which contains the master bitlines may be above a metal layer which contains the local bitlines.
[0024] The master bitlines may reside in the third metal layer and the local bitlines reside in the second metal layer.
[0025] The master bitlines may reside in the second metal layer and the local bitlines reside in the first metal layer.
[0026] The partitioned memory array may be suitable for use in SRAM, DRAM, EPROM and EEPROM memories.
[0027] Preferably the memory array is an SRAM and each local bitline is a local bitline pair and the master bitline is a master bitline pair.
[0028] Preferably a 4 Megabit SRAM is comprised of four local bitline pairs connected to a master bitline pair, each bitline pair having 128 memory cells.
[0029] Preferably the local bitlines may be recovered when its local select signal is selected while its corresponding master bitline is being recovered.
[0030] Preferably each local bitline has an equilibrate device which is controlled by an equilibration signal.
[0031] Preferably the equilibration signal is decoded based on its corresponding local select signal.
[0032] Preferably each local bitline has a precharge device which is controlled by a precharge signal.
[0034] According to a second preferred embodiment of the present invention there is provided a partitioned memory array, comprising a plurality of master bitlines, a plurality of local bitlines connected to a plurality of memory cells, a plurality of interface circuits, which connects each master bitline to at least two of the local bitlines and which provides for gain of a signal on the local bitlines or isolation of the capacitance of the local bitlines from the capacitance of the master bitlines, and a plurality of local select signals, each capable of selecting a corresponding local bitline to be coupled to its corresponding master bitline.
[0035] The local bitline may be connected to the master bitline through at least one select transistor and isolation of the capacitance of the local bitlines from the capacitance of the master bitlines is provided by at least one source-follower transistor.
[0036] The source of an n-channel select transistor may be connected to the master bitline, the gate is connected to a corresponding local select signal, and the drain is connected to an n-channel source follower transistor whose drain is connected to a supply voltage and whose gate is connected to the local bitline.
[0038] The drain of a p-channel select transistor may be connected to the master bitline, the gate is connected to a corresponding local select signal, and the source is connected to an n-channel source follower transistor whose drain is connected to a supply voltage and whose gate is connected to the local bitline.
[0040] The gate of the source follower transistor may be controlled by a pull-down transistor to ground and a pass gate which in turn is controlled by the local select signal, such that if the pass gate is not on, the source follower transistor is turned off, and if the pass gate is on, the source follower transistor is turned on.
[0041] Preferably a first local bitline and a second local bitline share a source follower transistor.
[0042] A first local bitline and a second local bitline may share a local select signal which provides a path to ground, with each local bitline having a transistor as its interface circuit.
[0045] Preferably a local bitline is selected when its corresponding local select signal is set to a first voltage level and is not selected when its corresponding local select signal is set to a second voltage level.
[0046] Preferably the first voltage level is a logic high and the second voltage level is a logic low.
[0050] The interface circuit may provide for the current differential of a selected memory cell to be amplified.
[0051] Preferably the current differential of a selected memory cell is amplified by a plurality of source follower transistors.
[0052] Preferably the current differential on a master bitline which is caused by source follower transistors is due to the resultant voltage differential on a corresponding local bitline when a memory cell is selected.
[0053] A cascode current sense amp may provide a virtual short across a local bitline pair, having a first local bitline and a second local bitline, such that the first local bitline and the second local bitline operate at the same voltage potential.
[0054] The first local bitline and the second local bitline may each have a first p-channel transistor whose gate is cross-coupled to the other local bitline and whose drain is connected to the source of a second p-channel transistor whose gate is connected to the local select signal and whose drain is connected to the master bitline.
[0055] The interface circuit of a local bitline which is not selected to be coupled to its corresponding master bitline may act as a load device for its corresponding master bitline.
[0056] Local bitline capacitance may be isolated from master bitline capacitance by clocking the source of a plurality of corresponding select transistors with the corresponding local select signal.
[0057] The source of a p-channel select transistor may be clocked by a local select signal, the gate is connected to the local bitline, and the drain is connected to the master bitline.
[0058] Isolation between a local bitline and a master bitline may be provided by a corresponding local select signal which is clocked to ground and acts as a current source when the local bitline is selected.
[0059] The gate of a transistor may be connected to the local bitline, the drain is connected to the master bitline and the source is connected to the local select signal.
[0060] Preferably at least two local bitlines share a dynamic sense amp, share a local select signal which clocks the dynamic sense amp, with each local bitline having an isolate signal to isolate the capacitance of the local bitline from the capacitance of the master bitline, and wherein the dynamic sense amp controls transistors connected to the master bitline.
[0061] Preferably when the isolate signal is a first predetermined voltage level, the local bitline is isolated, and when the isolate signal is a second predetermined voltage level, the local bitline is not isolated.
[0062] Preferably the first predetermined voltage level is Vcc and the second predetermined voltage level is 0 volts.
[0063] The interface circuit by which a local bitline is connected to its corresponding master bitline may have an n-channel pass gate.
[0064] Preferably the n-channel pass gate is driven by a write local select signal such that the pass gate conducts only during a write cycle.
[0065] During a write cycle, an inverter connected to a master bitline may cause a local bitline to be pulled to a predetermined voltage if its corresponding master bitline is at the predetermined voltage when the local bitline is selected.
[0068] Preferably a bias signal controlled by the column decode signal controls the load device such that only selected columns draw current.
[0069] Preferably a master bitline pair has a first master bitline and a second master bitline each of which has a transistor as its load device, wherein the gate of the first master bitline transistor is connected to the second master bitline and the gate of the second master bitline transistor is connected to the first master bitline.
[0070] Preferably the first master bitline and the second master bitline are connected to the load device which in turn is connected to a transistor which is controlled by a column decode signal and connected to a supply voltage.
[0072] The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
Figure 1 is a block diagram of a partitioned memory array according to the prior art;
Figure 2 is a schematic diagram of a portion of a partitioned memory array according to the present invention;
Figure 3a is a schematic diagram of a full CMOS transmission gate utilized as interface circuitry according to a first preferred embodiment of the present invention;
Figure 3b is a schematic diagram of an n-channel transistor utilized as interface circuitry according to a second preferred embodiment of the present invention;
Figure 4 is a schematic diagram of a partitioned memory array having interface circuitry and local bitline resistors, according to the present invention;
Figures 5 - 18 are schematic diagrams illustrating alternate preferred embodiments of interface circuitry, and master bitline loading devices, necessary for performing a read, according to the present invention; and
Figures 19 and 20 are schematic diagrams illustrating alternate preferred embodiments of interface circuitry necessary for performing a write, according to the present invention.
[0073] Referring to Figure 1, a block diagram of a partitioned memory array 10 according to the prior art is shown. As high speed memories, such as SRAMs, have become larger in density, there has been considerable emphasis placed on careful partitioning of the memory array to reduce the capacitance of bitline pairs, such as might be introduced by bitline pair 18, which must be driven by memory cells in the array.
[0074] As a result of this emphasis, memory array partitioning has increased in size and complexity. For example, memory arrays have increased the number of columns to four times the number of rows in an effort to reduce bitline capacitance. This is shown in Figure 1 where there are 4096 columns to 1024 rows, a configuration which is representative of a 4 Megabit SRAM. Also illustrated is the bisection of rows by column decoding and sense amp circuitry 14 into two row sections 12 and 16, each having 512 rows. While this methodology does yield a decrease in bitline capacitance, it may not be sufficient for memories of very high density and/or high speed.
[0075] Referring now to Figure 2, a schematic diagram of a portion of a partitioned memory array 20 according to the present invention is shown. A hierarchical bitline configuration is employed, whereby local bitline pairs, such as 22, 24, 26, and 28 are connected to master bitline 30 and its complement,
32. Local bitline pairs are composed of two bitlines which are the complement of each other, as is well understood in the art. Likewise, master bitline 30 and
32 together form a master bitline pair.
[0076] Continuing with the 4 Megabit SRAM example, the 512 cell bitline of Figure 1 is divided into four local bitline pairs 22, 24, 26, and 28 of 128 cells each. Each local bitline pair is separated from the other three local bitline pairs by interface circuitry 50 which is passive circuitry that connects a local bitline to master bitline 30 and
32. Local select signals 34, 36, 38, and 40 each couple an associated local bitline to master bitline 30 and
32. For example, local select signal 34 couples its local bitline 22 to master bitline 30 and 32.
[0077] As discussed above, a long bitline pair has been divided into four local bitline pairs; however, it is valid to break the bitline into any number of local bitline pair segments. The tradeoff to be considered is that while a larger number of segments would yield less capacitance and thus faster signal development, this would be done at the expense of additional layout area being consumed by an increased number of interface circuitry 50 and increased loading on the master bitline. However, if traditional architecture having an equal number of rows as columns is used and column decoding and sense amp circuitry 14 as shown in Figure 1 is placed at the edge of the memory array, then utilization of hierarchical architecture having master and local bitlines can result in layout area savings. This technique will utilize a smaller die than the prior art memory array of Figure 1 and will result in equal or better performance as measured by decreased bitline capacitance. The use of master bitlines allows for a smaller memory die even if the performance is the same.
[0078] For high density memories, three metal layers may be utilized to achieve layout savings and to render local and master bitlines and wordline control. For example, it may be desirable to place master wordlines and sub-master wordlines in the first metal layer M1, local bitlines in M2, and master bitlines in M3. Master bitlines can be placed on top of local bitlines or at an offset from local bitlines such that layout area is conserved and local bitline capacitance is reduced. A master bitline in M3 could be placed directly on top of its associated local bitline which resides in M2. The master bitline capacitance is primarily bussing capacitance of the highest level conductor, in this case M3, with virtually no junction capacitance except at interface circuitry 50. Therefore, if the master bitline 30 and
32 are placed over the local bitline, up to one-third of the bus would couple to itself; it is not necessary for the master bitline pair to be placed over the first local bitline pair 22 if sensing circuitry and master bitline control 52 is situated at the bottom as shown in Figure 2. The bitline capacitance that a memory cell must drive is reduced by as much as one-fourth the typical capacitance of the prior-art.
[0079] Due to the relative newness of a third metal layer, pitch control may not be as readily available for the third metal layer as for the first and second metal layers. Since master and sub-master wordlines typically do not require as much pitch control as master and local bitlines, an alternate utilization of metal layers is to place local bitlines in M1, master bitlines in M2 and master and sub-master wordlines in M3. This arrangement of metal layers may make the manufacturing process easier to control.
[0080] Local bitlines which are not selected by their respective local select signals should not be allowed to float at an undetermined voltage level for an indefinite period of time. A bitline pull-up transistor may be placed on each local bitline, but this solution requires a good amount of layout area, area which would be desirable to conserve as much as possible. As an alternative, a high value resistor may be formed in polysilicon 1, 2, or 3 layers, or in the active diffusion region to serve as a maintaining current source at the chosen voltage level, typically Vcc or Vcc - VT. High value resistors in the local bitlines may greatly reduce the layout area required for high density devices and prevent local bitlines from floating at undetermined voltage levels. Similarly, the master bitline may also have its own load device for facilitating read and write operations, whereby writing is performed using conventional methods and sensing may be accomplished using conventional voltage or current sensing techniques.
[0081] Interface circuity 50 may be implemented a variety of ways but it must allow the reading and writing of memory cells. Referring to Figures 3a and 3b, a schematic diagram of a full CMOS transmission gate and an n-channel transistor, respectively, are illustrated as interface circuitry according to a first and a second preferred embodiment of the present invention. The full CMOS transmission gate of Figure 3a has an n-channel transistor 62 and a p-channel transistor 64 which together connect the master bitline (MBL) to the local bitline (LBL). The gate of an n-channel transistor 62 is connected to local select signal LS, while the gate of p-channel transistor 64 is connected to the complement of the local select signal, LSn. An advantage of CMOS transmission gate 60 is the ease of reading and writing of memory cells it provides, especially when the LBL is biased at the supply voltage, usually Vcc. On the other hand, since CMOS transmission gate 60 is composed of two transistors, more layout area is required than if only a single transistor were used.
[0082] Figure 3b shows a second preferred embodiment of interface circuitry 66, using only a single n-channel transistor 68. An obvious advantage of n-channel transistor 68 is that only one transistor, not two, is used and thus less layout area is required. However, bootstrapping of the local select signal, LSn, may be required, especially if local bitline are biased at Vcc in order to avoid a VT drop across n-channel transistor 68. It may be possible to obviate the need for bootstrapping if n-channel transistor 68 has a natural VT (without implant) of 0.3. volts rather than a normal VT of approximately 0.65 volts and an n-channel pullup is used on the local bitline. Additionally, utilizing a pumped well in order to reduce body effect may also make bootstrapping unnecessary. It will be understood by one skilled in the art that, while a pumped well and a natural VT are not necessary, they are enhancements that may or may not be made.
[0083] Referring now to Figure 4, shown is a schematic diagram of a partitioned memory array 70 having n-channel transistor interface circuitry 84 and local bitline high value resistors 86 such that local bitlines do not float. . For simplicity, only two of the four local bitlines required for the 4 Megabit example are shown: local bitline pairs 72 and 74. Local bitline pairs 72 and 74 have high value resistors 86 which tie the local bitline pair to Vcc such that it does not float. A typical value for high value resistor 86 is 1 Megohm. The local bitline pairs are connected to master bitline 76 and master bitline 78 by n-channel transistors 84, comprising the interface circuitry 84. Local select signals 80 and 82 couple local bitlines 72 and 74, respectively, to master bitline 76 and master bitline 78. The use of n-channel transistor interface circuitry 84 and resistive load 86 greatly decreases the level of bitline capacitance which must be driven by memory cells 88 and ties the local bitlines to a predetermined voltage.
[0084] The recovery of local bitlines through precharge and/or equilibrate can be accomplished by leaving local select signals on while the master bitline pair is being recovered. If required, local bitline pairs could have their own equilibrate and/or precharge devices, such as a p-channel or other shorting transistor, where equilibrate is decoded based on local select signals. In addition, on a synchronous or pipelined device, multiple wordlines associated with different local bitlines could be selected at the same time, if advantageous. This would allow independent development of signals on each local bitline, where the clocking of local select signals are performed at the appropriate time. This would, of course, increase the power consumption level. However, if signal swing on the local bitlines is reduced, equilibrate and/or precharge may be avoided entirely, except at the end of a write cycle. Thus, circuitry needed for equilibrate and/or precharge functions would be reduced or eliminated.
[0085] Interface circuitry may be implemented a variety of ways but it must allow for the reading and writing of memory cells. Additionally, it is desirable to explore interface circuitry options which provide voltage gain and/or isolation while connecting local bitlines to master bitlines. Figures 5-18, schematic diagrams illustrating alternate preferred embodiments of interface circuitry necessary for performing a read, according to the present invention, are shown.
[0086] Referring now to Figure 5 interface circuitry 100 is shown. Local bitline pair LBLn and LBLn are connected to master bitline pair MBL and
via source follower transistors 102 and select transistors 104. While the select transistors 104 are shown as n-channel devices, they could also be p-channel transistors. The local select signal LSn is used to select one local bitline pair to control the master bitline pair. This option works particularly well when local bitlines are biased at Vcc. Source follower transistors 102 are advantageous in that they provide a shifting mechanism for MBL and
which allows an optimum common mode voltage for sensing MBL and
to be provided. Master bitline pair MBL and
are then sensed by a separate sense amplifier.
[0087] The gain provided by source follower transistors 102 may be close to unity, depending on the master bitline load used, but a high current drive or transconductance may be instead achieved, which is desirable when driving large capacitances. Unlike interface circuitry for a passive hierarchical bitline structure, interface circuitry for an active hierarchical bitline structure is comprised of active components which amplify the local bitline voltage or current differential developed by the selected memory cell. In addition, the local bitline capacitance is isolated from the master bitline capacitance. Thus, the local bitline capacitance is basically the only capacitance the memory cell must drive. Also, unlike the prior art where SRAMS typically have passgates in the column decode path, the local bitline signal does not go through passgates which can retard signal development.
[0088] A variety of master bitline load devices exists for hierarchical bitline structures. Figures 6a-6d illustrate load devices which offer varying degrees of gain which may be achieved. These load devices may be controlled by a column decode signal. Referring to Figure 5a, the master bitline pair has as load devices n-channel transistors 112. N-channel transistors 112 are controlled by the Bias signal and are biased at a DC voltage above a threshold voltage level. The Bias signal may be a column decode signal, such that only selected columns draw current. In this way, current and therefore power dissipation is greatly reduced. An additional advantage of load device 110 is that few transistors are used. For simplicity, column decode control circuitry is not shown.
[0089] Figure 6b illustrates n-channel load transistors 122, the gate of which is tied to the master bitline. Unlike the load device 110 of Figure 6a, no biasing is provided and gain may be reduced. Referring to Figure 6c, a third type of master bitline loading device 130 is shown. The gates of N-channel load transistors 132 are tied to the opposite master bitline as shown. This configuration offers greater gain than the load devices of Figures 6a and 6b, but does introduce feedback which may result in varying degrees of device latching. Referring to Figure 6d, a similar load device 140 with column decode control is shown. MBL and
are tied to n-channel transistor 142 which has column decode signal COL has its gate input.
[0090] While the master bitline load devices of Figures 6a-6d are described in conjunction with the interface circuitry of Figure 5, it will be understood by one skilled in the art that these load devices are equally well suited for other interface circuitry options, such as those which will now be described. An advantage of the load devices of Figures 6a-6d is that they have only a small number of transistors, effectively allowing for a smaller layout area.
[0091] The circuitry 150 of Figure 7 connects two different local bitlines LBLm and LBLn to master bitline pair MBL and
by combining interface circuitry. Adjacent interface circuitry, n-channel transistors 152, is utilized to minimize transistor count. Even though both local bitline LBLm and local bitline LBLn will affect master bitline pair MBL and
at the same time, only column m or n will have a voltage differential from the supply voltage, which is typically 5 volts. Therefore, the current differential of n-channel source follower transistors 154 is comparable to that of source-follower transistors 102 of Figure 5. However, the current differential expressed as a percent of total source-follower current is half that of Figure 5.
[0092] Interface circuitry 160 of Figure 8 uses one less transistor than circuitry 100 of Figure 5-Two select transistors have been replaced by n-channel select transistor 162, the gate of which is connected to local select signal LSn. Select transistor 162 and source-follower transistors 164 are n-channel, but may also be p-channel transistors. Master bitline pair MBL and
may get clamped by unselected local bitline transistors, depending on the voltage of the master bitline pair.
[0093] Figure 9 illustrates interface circuitry 170 in which only one local bitline will have a voltage differential from the supply voltage. This is similar to the voltage differential discussed in Figure 7. Again, only one local bitline will have a voltage differential, and the total current differential on the master bitline pair caused by source follower transistors 172 is due to the resultant voltage differential when a memory cell is selected. The differential expressed as a percentage of total current may be reduced depending on the number of local bitline segments that exist. Thus, the percentage may be lower than that possible with the Figure 7 option. Additionally, during write cycles, source follower transistors 172 must be weak enough to be initially overcome; in the other interface circuitry option previously discussed, it is permissible to have the transistors turned off during a write cycle. A advantage of interface circuitry 170 is the small number of transistors required.
[0094] A major advantage of the interface circuitry 180 of Figure 15 is that local bitline pairs, such as LBLn and
, which are not selected by local select signal LSn are not isolated from the master bitline pair MBL and
but instead form the loads for the master bitline pair. The drain of local bitline transistors 182 are clocked. A local bitline is selected when local select signal LS is high and is deselected when it is low.
[0095] Because local bitline transistors 182 act as master bitline loading devices when deselected, the load devices described in Figures 6a-6d are not necessary for interface circuitry 180. A disadvantage to this approach is that the current drawn through the loading devices is not controlled by column decoding or any other signal.
[0096] Referring to Figure 11, another interface circuitry option 190 is shown. As in Figure 7, interface circuitry is combined for two adjacent local bitline pair segments: LBLm and LBLn. This approach results in fewer transistors being used than if the two adjacent local bitline pair segments did not share interface circuitry. Master bitline pair MBL and
has no series devices on source follower transistors 192, but the memory cell sees a pass gate. When selecting a local bitline, the appropriate local select signal goes to a logic low voltage level.
[0097] For the interface circuitry 200 shown in Figure 12, it is necessary for the local bitline pair LBLn and
to be biased below Vcc - |VTp|, such as Vcc - VTn-body. The sources of local bitline p-channel transistors 202 are clocked such that the selected local bitline segment has local select signal LS high and the deselected local bitline segment has local select signal LS low. In other words, as long as the master bitline pair is biased below Vcc - VTn-body +|VTp-body|and VTn-body > |VTp|, the unselected segments will be isolated from the master bitline pair. Also, as long as the master bitline pair is biased at or below Vcc - [VTn-body - VTp], p-channel local bitline transistors 202 will be in saturation. For the above equations, Vcc is the supply voltage, VTp-body and VTn-body are the body effect threshold voltages of p-channel and n-channel transistors, respectively.
[0098] In Figure 12, p-channel transistors and biasing of local bitlines at Vcc - VTn-body are described and can be used with any other interface circuitry explored in Figures 2 through 10 above.
[0099] The interface circuitry described above has been biased at a supply voltage such as Vcc or Vcc-VT. It is also possible to have circuitry which is tied to ground. Referring to Figure 12, interface circuitry 210 connects local bitline pair LBLn and LBLn to master bitline pair MBL and MBL but is biased to ground as shown. Source coupled n-channel transistors 212 are used to interface local bitlines to the master bitline; local bitline pair LBLn and LBLn is selected when LSn is a logic high voltage level. Local bitlines may be biased at Vcc ₋ VTn with the master bitline load devices, examples shown in Figure 14, such as high value resistors or p-channel transistors, connected to Vcc.
[0100] Referring to Figures 14a-14d several different master bitline loading devices are shown. As in Figures 6a-6d these load devices may easily be controlled by a column decode signal such that only selected columns would draw current, thereby reducing current and power consumption. Referring to Figure 14a, the master bitline pair has as load devices p-channel transistors 222. P-channel transistors 222 are controlled by the Bias signal and are biased at a DC voltage below Vcc -|VTp|. The Bias signal may be a column decode signal, such that only selected columns draw current. The Bias signal is a logic high voltage level when the column is unselected. In this way, current and therefore power dissipation is greatly reduced. An additional advantage of load device 220 is that few transistors are used. For simplicity, column decode control circuitry is not shown.
[0101] Figure 14b illustrates p-channel load transistors 232, the gate of which is tied to the master bitline. Unlike the circuitry 220 of Figure 14a, no biasing is provided and gain may be relatively small. Referring to Figure 14c, a third type of master bitline loading device 240 is shown. The gates of p-channel load transistors 242 are tied to the opposite master bitline as shown. This configuration offers greater gain than the load devices of Figures 14a-14b, but also introduces feedback which may result in varying degrees of device latching. Referring to Figure 14d, a similar load device 250 with column decode control is shown. P-channel transistor 254 has column decode signal COL as its gate input. Resistors, biased to Vcc, could also be used as master bitline load devices.
[0102] While the master bitline load devices of Figures 14a-14d are described in conjunction with the interface circuitry of Figure 13, it will be understood by one skilled in the art that these load devices are equally well suited for other interface circuitry options, such as those which will now be described.
[0103] Referring to Figure 13,the current source transistor used in other interface circuits is not included to minimize transistors used. Instead the local select signal LSn, which is clocked to ground, acts as a current source. Local bitline pair LBLn and
are connected to local bitline transistors 262 which are connected to master bitline pair MBL and
An advantage of this interface circuitry is that the transistor count is low.
[0104] Figure 15 illustrates interface circuitry 270 which is similar to that shown in Figure 13 but that adjacent local bitline segments combine interface circuitry in order to save on transistor count. Interface circuitry 270 connects local bitline pairs LBLn,
, LBLm, and
to master bitline pair MBL and
but is biased to ground as shown. N-channel transistors 272 are used to interface local bitlines to the master bitline. While transistors 272 are connected serially, they may also be placed in parallel to each other. Local bitlines may be biased at Vcc - VTn with the master bitline loads such as high value resistors or p-channel transistors, connected to Vcc.
[0105] Local bitline segments which are not selected by local select signal LSm+n will have no differential voltage from ground, such that the differential voltage on the master bitline pair will be due to the differential which exists at the local bitline pair which is selected.
[0106] Referring to the interface circuit 280 of Figure 17, adjacent local bitline segments LBLm and LBLn share a dynamic sense amp, comprised of n-channel transistors 282, clocked by local select signal LSm+n. Again, the sharing of interface circuitry allows transistor count to be minimized. Also, having one local select signal LSm+n means less signals are needed. P-channel transistors 284 may be replaced by n-channel devices if sense nodes 286 are inverted.
[0107] Isolation input signals ISOm and ISOn allow local bitline LBLm or LBLn to be isolated. By setting ISOm to a logic high voltage level such as 5 volts, local bitline pair LBLm and
are effectively isolated from other device circuitry; similarly, when ISOn is set to a logic low voltage level such as 0 volts, local bitline pair LBLn and
are not isolated from the dynamic sense amplifier. For example, LSm+n is clocked low to sense data and ISOn is then clocked high to isolate the sense amplifier from local bitline LBLn.
[0108] Finally, Figure 18 illustrates interface circuitry 290 which employs a cascode current sense amp to provide a virtual short across local bitline pair LBLn and
if p-channel transistors 292 are biased properly, i.e. at saturation. Thus, the current difference between the series paths formed by p-channel transistors 292 and 294 is the memory cell current. As with other interface circuits, various load devices, such as those shown in Figures 6a-6d may be utilized.
[0109] In addition to the interface circuitry discussed in Figure 18 it is possible to use other forms of cascade and/or cascode voltage and current sensing to achieve voltage gain. Another option which may enhance manufacturability is to lay interface circuitry out on multiple column pitch with multiple local select signals decoded by column addresses.
[0110] Up to now, the interface circuitry options discussed have been suitable for performing a read, but have not provided connection between the master bitline pair and local bitline pairs suitable for performing a write. Referring to write circuitry 300 of Figure 19, n-channel passgate 302 conducts only during a write cycle. Write local select signal WLSn will go to a logic high voltage level only during a write cycle and only if the row address points to a row associated with that particular local bitline, in this case LBLn. A memory cell is written by driving the appropriate master bitline pair low and turning on the write local select n-channel transistors 302 such that the local bitline may be pulled to a low logic level.
[0111] As mentioned previously, recovery through precharging of the local bitlines may be achieved by precharing the master bitline pair and pulsing the write local select signal WLSn to connect the local bitline pair to its associated master bitline pair. Also, it may be necessary to have an equilibrate device on the local bitline pair in order to short together the two local bitlines comprising a bitline pair: for instance, LBLn and
. If any equilibrate signal is required, it could be decoded using a local select signal.
[0112] Local bitlines which are not selected during a write cycle can not be allowed to float for an indefinite period of time. As mentioned earlier, a pull-up transistor or high value resistor may be required for each local bitline. For instance, an interface circuitry option calling for biasing of the local bitlines to Vcc - VT may utilize a high value resistor which is also connected to a Vcc - VT level. Alternately, if a pull-up transistor which is strong enough to clamp the local bitline voltage differential to a small value is used, recovery of the line through equilibration may not be required between read cycles even though recovery may be required after a write cycle.
[0113] Another option for write circuitry is shown in Figure 20. Local bitline transistors 312 control local bitline pair LBLn and
. Circuitry 310 performs such that the master bitline pair is at or near Vcc during a read cycle. However, during a write cycle, inverters 314 cause either LBL or
to be pulled to ground through local select transistor 316 based on either MBL or
being at ground. An advantage of this circuitry over that of Figure 19 is that a separate write local select signal WLSn is not required.
[0114] The hierarchical bitline memory architecture described above is useful for asynchronous, synchronous and pipelined memory devices such as SRAMs, DRAMs, EPROMs and EEPROMs. It is particularly useful on high density, high performance devices such as the 4 Megabit SRAM, 16 Megabit SRAM and larger devices, to reduce the effective bitline capacitance a memory cell must drive. The speed advantage which could be realized with the hierarchical memory architecture would depend on the density of the device and the number of partitions of the bitline into local bitlines (at the expense of area) but could be on the order of several nanoseconds. The ability to choose various kinds of interface circuitry for use in hierarchical bitline memory architecture allows for the control of characteristics such as voltage gain and/or isolation. Control of these characteristics allows for an active hierarchical bitline memory architecture. control of characteristics such as voltage gain and/or isolation. Control of these characteristics allows for an active hierarchical bitline memory architecture.
[0115] While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. For instance, local bitline pairs have been described in conjunction with the 4 Megabit SRAM embodiment, but one skilled in the art will appreciate that while other high density memories such as DRAMs, EPROMs, and EEPROMs have bitlines, not bitline pairs, the spirit and scope of the invention will not be affected. Additionally, the placement of the master bitlines in the third metal layer and local bitlines in the second metal layer is only one possible way to implement device metallization. Also, master and sub-master wordlines, master bitlines, and local bitlines could be placed in any conductive material such as metal or polysilicon.
1. A partitioned memory array, comprising:
a plurality of master bitlines;
a plurality of local bitlines connected to a plurality of memory cells;
a plurality of interface circuits, which connects each master bitline to at least two of the local bitlines; and
a plurality of local select signals, each capable of selecting a corresponding local bitline to be coupled to its corresponding master bitline.
a plurality of master bitlines;
a plurality of local bitlines connected to a plurality of memory cells;
a plurality of interface circuits, which connects each master bitline to at least two of the local bitlines; and
a plurality of local select signals, each capable of selecting a corresponding local bitline to be coupled to its corresponding master bitline.
2. The memory array of claim 1, wherein each local select signal controls one interface
circuit for each master bitline.
3. The memory array of claim 1, wherein the interface circuitry is comprised of an n-channel
transistor.
4. The memory array of claim 3, wherein the local select signals are bootstrapped above
a first supply voltage.
5. The memory array of claim 3, wherein the n-channel transistor has a lower VT such that the voltage drop across it is minimised.
6. The memory array of claim 3, wherein the well in which the n-channel transistor resides
is pumped to a lower voltage which is less than a second supply voltage.
7. The memory array of claim 1, wherein each local bitline is connected to a loading
element such that it is tied to a predetermined voltage level.
8. A partitioned memory array, comprising:
a plurality of master bitlines;
a plurality of local bitlines connected to a plurality of memory cells;
a plurality of interface circuits, which connects each master bitline to at least two of the local bitlines and which provides for gain of a signal on the local bitlines or isolation of the capacitance of the local bitlines from the capacitance of the master bitlines; and
a plurality of local select signals, each capable of selecting a corresponding local bitline to be coupled to its corresponding master bitline.
a plurality of master bitlines;
a plurality of local bitlines connected to a plurality of memory cells;
a plurality of interface circuits, which connects each master bitline to at least two of the local bitlines and which provides for gain of a signal on the local bitlines or isolation of the capacitance of the local bitlines from the capacitance of the master bitlines; and
a plurality of local select signals, each capable of selecting a corresponding local bitline to be coupled to its corresponding master bitline.
9. The memory array of claim 8, wherein the local bitline is connected to the master
bitline through at least one select transistor and isolation of the capacitance of
the local bitlines from the capacitance of the master bitlines is provided by at least
one source-follower transistor.
10. The memory array of claim 9, wherein the source of an n-channel select transistor
is connected to the master bitline, the gate is connected to a corresponding local
select signal, and the drain is connected to an n-channel source follower transistor
whose drain is connected to a supply voltage and whose gate is connected to the local
bitline.
11. The memory array of claim 9, wherein the drain of a p-channel select transistor is
connected to the master bitline, the gate is connected to a corresponding local select
signal, and the source is connected to an n-channel source follower transistor whose
drain is connected to a supply voltage and whose gate is connected to the local bitline.
12. The memory array of claim 8, wherein the interface circuit of a local bitline which
is not selected to be coupled to its corresponding master bitline acts as a load device
for its corresponding master bitline.
13. The memory array of claim 8, wherein at least two local bitlines share a dynamic sense
amp, share a local select signal which clocks the dynamic sense amp, with each local
bitline having an isolate signal to isolate the capacitance of the local bitline from
the capacitance of the master bitline, and wherein the dynamic sense amp controls
transistors connected to the master bitline.
14. The memory array of claim 8, wherein the memory array is formed using a first metal
layer, a second metal layer, and a third metal layer.
15. The memory array of claim 1 or claim 8, wherein one of the local bitlines may be recovered
when its local select signal is selected while its corresponding master bitline is
being recovered.
16. The memory array of claim 1 or claim 8, wherein each local bitline has a precharge
device which is controlled by a precharge signal.
17. The memory array of claim 8, wherein the master bitlines each have a load device which
is connected to a supply voltage.