BACKGROUND OF THE INVENTION
1. Field of the Invention:
[0001] The present invention relates to a driving circuit for a display apparatus. More
particularly, the present invention relates to a driving circuit for an active matrix
type liquid crystal display apparatus which displays an image with multiple gray scales
in accordance with digital video signals.
2. Description of the Related Art:
[0002] An active matrix type liquid crystal display apparatus includes a display panel and
a driving circuit for driving the display panel. The display panel includes a pair
of glass substrates and a liquid crystal layer formed between the pair of glass substrates.
On one of the pair of glass substrates, a plurality of gate lines and a plurality
of data lines are formed. The driving circuit is disposed for every pixel in the display
panel, and the driving circuit applies a driving voltage to the liquid crystal of
the display panel. The driving circuit includes a gate driver for individually selecting
one of a plurality of switching elements connected to the gate lines and the data
lines, and a data driver for supplying a video signal corresponding to an image to
pixel electrodes via the selected switching element.
[0003] Figure 11 shows a configuration of a part of a data driver in a prior art driving
circuit. The circuit 110 shown in Figure 11 outputs a video signal to one of a plurality
of data lines. Accordingly, the data driver requires circuits 110 the number of which
is equal to the number of data lines provided in a display panel. For simplicity of
explanation, it is herein assumed that video data consists of three bits (Do, D
1, D
2). On such an assumption, the video data may have eight values of 0 to 7, and a signal
voltage supplied to each pixel is one of eight levels V
O-V
7.
[0004] The circuit 110 includes a sampling flip-flop M
SMP, a holding flip-flop M
H, a decoder DEC, and analog switches ASW
O-ASW
7. To each of the analog switches ASW
O-ASW
7, a corresponding one of external source voltages V
O-V
7 of respective eight levels which are different from each other is supplied. In addition,
to the analog switches ASW
0-ASW
7, control signals SO-S
7 are supplied from the decoder DEC, respectively. Each of the control signals SO-S
7 is used for switching the ON/OFF state of the analog switch.
[0005] Next, the operation of the circuit 110 is described. At the rising of a sampling
pulse T
SMPn corresponding to the nth pixel, the sampling flip-flop M
SMP gets video data (Do, D
1, D
2), and holds the video data therein. When such video data sampling for one horizontal
period is completed, an output pulse signal OE is applied to the holding flip-flop
M
H. Upon receiving the output pulse signal OE, the holding flip-flop M
H gets the video data (Do, D
1, D
2) from the sampling flip-flop M
SMP, and transfers the video data to the decoder DEC.
[0006] The decoder DEC decodes the video data (Do, D
1, D
2), and produces a control signal for turning on one of the analog switches ASW
O-ASW
7 in accordance with the respective values (0-7) of the video data (Do, D
1, D
2). As a result, one of the external source voltages V
O-V
7 is output to a data line On. For example, in the case where the value of the video
data held in the holding flip-flop M
H is 3, the decoder DEC outputs a control signal S
3 which turns on the analog switch ASW
3. As a result, the analog switch ASW
3 becomes into the ON-state, and V
3 of the external source voltages V
O-V
7 is output to the data line On.
[0007] Such a prior art data driver involves a problem in that, as the number of bits in
video data increases, the circuit configuration becomes complicated and the size of
the circuit is increased. This is because the prior art data driver requires gray-scale
voltages the number of which is equal to the gray scales to be displayed. For example,
in the case where the video data consists of 4 bits for displaying 16 gray-scale images,
the number of required gray-scale voltages is: 2
4 = 16. Similarly, in the case where the video data consists of 6 bits for displaying
64 gray-scale images, the number of required gray-scale voltages is: 2
6 = 64. In the case of 8-bit video data for displaying 256 gray-scale images, the number
of required gray-scale voltages is: 2
8 = 256. As described above, the prior art data driver requires a large number of gray-scale
voltages as the number of bits of video data increases. This causes the circuit configuration
to be complicated and the circuit size to be increased. Moreover, interconnections
between voltage source circuits and analog switches are also complicated.
[0008] For the above-mentioned reasons, the actual application of such a prior art data
driver is limited to 3-bit video data or 4-bit video data.
[0009] In order to solve such prior art problems, there have been proposed methods and circuits
for driving a display apparatus in Japanese Laid-Open Patent Publication Nos. 4-136983,4-140787,
and 6-27900. Please note that Japanese Laid-Open Patent Publication No. 6-27900 is
nota priorart reference of this application, because Japanese Laid-Open Patent Publication
No. 6-27900 was laid-open on February 4, 1994.
[0010] Figure 12 shows a configuration for a part of a driving circuit disclosed in Japanese
Laid-Open Patent Publication No. 6-27900. The circuit 120 shown in Figure 12 outputs
a video signal to one of a plurality of data lines. Accordingly, the data driver requires
circuits 120 the number of which is equal to the number of data lines provided in
a display panel. It is herein assumed that video data consists of 6 bits (Do, D
1, D
2, D
3, D
4, D
5). On such an assumption, the video data may have 64 values of 0-63, and a signal
voltage applied to each pixel is one of nine gray-scale voltages Vo, V
8, V
16, V
24, V
32, V
40, V
48, V
56, and V
64, and a plurality of interpolated voltages which are produced from the gray-scale
voltages V
o, V
8, V
16, V
24, V
32, V
40, V
48, V
56, and V
64.
[0011] The circuit 120 includes a sampling flip-flop M
SMP, a holding flip-flop M
H, a selection control circuit SCOL, and analog switches ASW
0-ASW
8. To each of the analog switches ASW
0-ASW
8, a corresponding one of gray-scale voltages Vo, V
8, V
16, V
24, V
32, V
40, V
48, V
56, and V
64 of respective levels which are different from each other. To the analog switches
ASW
0-ASW
8, control signals So, S
8, S
16, S
24, S
32, S
40, S
48, S
56, and S
64 are su
p- plied from the selection control circuit SCOL, respectively. Each of the control
signals are used to switch the ON/OFF state of the analog signal.
[0012] To the selection control circuit SCOL, clock signals t
1, t
2, t
3, and t
4 are supplied. As is shown in Figure 13, the clock signals t
1, t
2, t
3, and t
4 have duty ratios which are different from each other. The selection control circuit
SCOL receives 6-bit video data d
5, d
4, d
3, d
2, d
1, and do, and outputs one of control signals So, S
8, S
16, S
24, S
32, S
40, S
48, S
56, and S
64 in accordance with the value of the received video data. The relationship between
the input and the output of the selection control circuit SCOL is determined by using
a logical table.
[0013] Table 1 shows a logical table for the selection control circuit SCOL. The 1st to
6th columns of Table 1 indicate values of bits d
5, d
4, d
3, d
2, d
1, and do of the video data, respectively. The 7th to 15th columns of Table
1 indicate values of control signals So, S
8, S
16, S
24, S
32, S
40, S
4ε, S
56, and S
64, respectively. Each blank in the 7th to 15th columns in Table 1 means that the value
of the control signal is 0. In addition, "t
i" indicates that the value of the control signal is 1 when the value of the clock
signal t
i is 1, and the value of the control signal is 0 when the value of the clock signal
t
i is 0. Also, "t
i" indicates that the value of the control signal is 0 when the value of the clock
signal t
i is 1, and the value of the control signal is 1 when the value of the clock signal
t
i is 0. Herein, i = 1, 2, 3, and 4.

[0014] As is seen from Table 1, when the value of the video data is a multiple of 8, one
of the gray-scale voltages V
o, ..., V
64 is output to the data line On. When the value of the video data is not a multiple
of 8, an oscillating voltage which oscillates between a pair of gray-scale voltages
V
o, ..., V
64 at a duty ratio of one of the clock signals t
1, t
2, t
3, and t
4 is output to the data line On. The data driver 120 produces seven different oscillating
voltages between respective adjacent gray-scale voltages, in accordance with the logical
table of Table 1. Thus, it is possible to attain 64 gray-scale images by using only
9 levels of gray-scale voltages.
[0015] The following equations are logical equations which define the relationships among
the video data d
5, d
4, d
3, d
2, d
1, and do, the clock signals t
1, t
2, t
3, and t
4, and the control signals So, S
8, S
16, S
24, S
32, S
40, S
4ε, S
56, and S
64 shown in Table 1.



[0016] Similarly, the control signals S
24, S
32, S
40, and S
48 are defined. The control signals S
56 and S64 are defined as follows.


[0017] In the above equations, {i} indicates a value when the binary data (d
5, d
4, d
3, d
2, d
1, do) is represented in the decimal notation. For example, {1} = (d
5, d
4, d
3, d
2, d
1, do) = (0, 0, 0, 0, 0, 1). In addition, "t
i" indicates a signal which is inverted from the signal t.
[0018] On the basis of the above logical equations, logical circuits shown in Figures 14
and 15 are obtained. The selection control circuit SCOL is constructed by the logical
circuits shown in Figures 14 and 15.
[0019] The logical circuit shown in Figure 14 produces 64 kinds of gray-scale selection
data {0} - {63} in accordance with the value of 6-bit video data (d
5, d
4, d
3, d
2, d
1, do). The logical circuit shown in Figure 15 produces control signals So, S
8, S
16, S
24, S
32, S
40, S
48, S
56, and S64, based on the gray-scale selection data {0} - {63} and the clock signals
t
1, t
2, t
3, and t
4. For example, a case where the video data (d
5, d
4, d
3, d
2, d
1, do) = (0, 0, 0, 0, 0, 1) is input to the selection control circuit SCOL is explained.
In such a case, the logical circuit shown in Figure 14 outputs the gray-scale selection
data {1}. The logical circuit shown in Figure 15 receives the gray-scale selection
data {1} and alternately outputs the control signal So and the control signal S
8 at a duty ratio of the clock signal t
1. As a result, the gray-scale voltage V
o and the gray-scale voltage V
8 are alternately output via the analog switch ASW
o and the analog switch ASW
s at the duty ratio of the clock signal t
1 to the data line On.
[0020] The actual data driver requires the selection control circuits SCOL the number of
which is equal to the number of data lines. Thus, the circuit scale of the selection
control circuit SCOL largely affects the chip size of the integrated circuit on which
the data driver is installed. If the circuit scale of the selection control circuit
SCOL becomes large, the cost for the integrated circuit is increased. Moreover, if
the number of bits of video data increases in order to realize an image with a larger
number of gray scales, the circuit scale of the data driver is further increased.
This also increases the size and the production cost of the integrated circuit.
SUMMARY OF THE INVENTION
[0021] The driving circuit of this invention is used for driving a display apparatus including
pixels and data lines for applying voltages to the pixels and which displays an image
with multiple gray scales in accordance with video data consisting of a plurality
of bits. The driving circuit includes: oscillating voltage specifying means for specifying
one of a plurality of oscillating signals having respective duty ratios which are
different from each other in accordance with video data consisting of bits selected
from the plurality of bits, and for outputting the specified oscillating signal T
and an oscillating signal T which is obtained by inverting the specified oscillating
signal T; gray-scale voltage specifying means for producing gray-scale voltage specifying
signals which specify a first gray-scale voltage and a second gray-scale voltage among
a plurality of gray-scale voltages supplied from gray-scale voltage supply means,
in accordance with video data consisting of bits other than the selected bits of the
plurality of bits; and output means for outputting the first gray-scale voltage and
the second gray-scale voltage specified by the gray-scale voltage specifying signals
to the data lines, in accordance with the oscillating signal T and the oscillating
signal T.
[0022] In one embodiment of the invention, the first gray-scale voltage and the second gray-scale
voltage are adjacent ones of the plurality of gray-scale voltages.
[0023] In another embodiment of the invention, the plurality of oscillating signals include
oscillating signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7,
respectively.
[0024] According to another aspect of the invention, a driving circuit for driving a display
apparatus including pixels and data lines for applying voltages to the pixels and
which displays an image with multiple gray scales in accordance with video data consisting
of a plurality of bits is provided. The driving circuit includes: control signal generating
means for generating a plurality of control signals in accordance with video data
consisting of a plurality of bits; and a plurality of switching means, each of the
plurality of switching means being supplied with a corresponding one of the plurality
of control signals and a corresponding one of a plurality of gray-scale voltages generated
by gray-scale voltage generating means, the gray-scale voltage supplied to the switching
means being output to the data lines via the switching means in accordance with the
control signal, wherein the control signal generating means includes: oscillating
voltage specifying means for specifying one of a plurality of oscillating signals
having respective duty ratios which are different from each other in accordance with
video data consisting of bits selected from the plurality of bits, and for outputting
the specified oscillating signal T and an oscillating signal T which is obtained by
inverting the specified oscillating signal T; gray-scale voltage specifying means
for producing gray-scale voltage specifying signals which specify a first gray-scale
voltage and a second gray-scale voltage among the plurality of gray-scale voltages,
in accordance with video data consisting of bits other than the selected bits of the
plurality of bits; and output means for outputting a first control signal which oscillates
at substantially the same duty ratio as that of the oscillating signal T to one of
the switching means which is supplied with the first gray-scale voltage specified
by the gray-scale voltage specifying signals and for outputting a second control signal
which oscillates at substantially the same duty ratio as that of the oscillating signal
T to one of the switching means which is supplied with the second gray-scale voltage
specified by the gray-scale voltage specifying signals.
[0025] In one embodiment of the invention, the first gray-scale voltage and the second gray-scale
voltage are adjacent ones of the plurality of gray-scale voltages.
[0026] In another embodiment of the invention, the plurality of oscillating signals include
oscillating signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7,
respectively.
[0027] In another embodiment of the invention, the switching means is an analog switch.
[0028] According to the driving circuit of the invention, a pair of gray-scale voltages
are selected (specified) among a plurality of gray-scale voltages, and one of a plurality
of oscillating signals is specified. The driving circuit outputs a voltage signal
which oscillates between the specified pair of gray-scale voltages at the oscillating
frequency of the specified oscillating signal. Therefore, a plurality of interpolated
gray scales can be realized between a plurality of applied gray-scale voltages.
[0029] According to the driving circuit of the invention, by using the gray-scale voltage
specifying means and the oscillating signal specifying means, it is possible to always
realize an image display with multiple gray scales in both cases where the driving
circuit directly outputs one of the plurality of gray-scale voltages and where the
driving circuit alternately outputs the specified pair of gray-scale voltages.
[0030] Accordingly, it is unnecessary to provide an additional driving circuit depending
on the cases where the driving circuit directly outputs one of the plurality of gray-scale
voltages and where the driving circuit alternately outputs the specified pair of gray-scale
voltages. As a result, it is possible to simplify the configuration of the driving
circuit, and the size of the driving circuit can be minimized.
[0031] Thus, the invention described herein makes possible the advantage of providing a
driving circuit for a display apparatus, which has a simplified and small construction,
and which can display an image with multiple gray scales in accordance with multi-bit
video data.
[0032] This and other advantages of the present invention will become apparent to those
skilled in the art upon reading and understanding the following detailed description
with reference to the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0033]
Figure 1 is a diagram showing a construction of a liquid crystal display apparatus.
Figure 2 is a timing chart illustrating the relationship among input data, sampling
pulses, and an output pulse in one horizontal period.
Figure 3 is a timing chart illustrating the relationship among input data, an output
pulse, an output voltage, and a gate pulse in one vertical period.
Figure 4 is a timing chart illustrating the relationship among input data, an output
pulse, an output voltage, a gate pulse, and a voltage applied to a pixel in one vertical
period.
Figure 5 shows waveforms of an output voltage oscillating in one output period.
Figure 6 is a diagram showing a part of a configuration for a data driver in a driving
circuit in an example according to the invention.
Figure 7 is a diagram showing a part of a configuration of a selection control circuit
SCOL in the driving circuit in the example according to the invention.
Figure 8 is a diagram showing another part of the configuration of the selection control
circuit SCOL in the driving circuit in the example according to the invention.
Figure 9 is a diagram showing another part of the configuration of the selection control
circuit SCOL in the driving circuit in the example according to the invention.
Figure 10 is a diagram showing another part of the configuration of the selection
control circuit SCOL in the driving circuit in the example according to the invention.
Figure 11 is a diagram showing a part of a configuration for a data driver in a conventional
driving circuit.
Figure 12 is a diagram showing a part of a configuration of a data driver in a driving
circuit of a related art.
Figure 13 shows waveforms of signals tl-t4 supplied to a selection control circuit SCOL.
Figure 14 is a diagram showing a part of a configuration of a selection control circuit
SCOL in the conventional driving circuit.
Figure 15 is a diagram showing another part of the configuration of a selection control
circuit SCOL in the conventional driving circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0034] Hereinafter, the present invention will be described by way of illustrative examples
in accordance with the accompanying drawings. In the following description, a matrix
type liquid crystal display apparatus is used as an example of a display apparatus.
It is appreciated that the present invention is applicable to other types of display
apparatus.
[0035] Figure 1 shows a construction of a matrix type liquid crystal display apparatus.
The liquid crystal display apparatus shown in Figure 1 includes a display section
100 for displaying a video image, and a driving circuit 101 for driving the display
section 100. The driving circuit 101 includes a data driver 102 which provides video
signals to the display section 100 and a scanning driver 103 which provides scanning
signals to the display section 100. The data driver may be called "a source driver"
or "a column driver". The scanning driver may be called "a gate driver" or "a row
driver".
[0036] The display section 100 includes an M x N array of pixels 104 (M pixels in each column
and N pixels in each row; where M and N are positive integers), and also includes
switching elements 105 respectively connected to the pixels 104.
[0037] In Figure 1, N data lines 106 are used for connecting respective output terminals
S(i) (i = 1, 2, ...,N) of the data driver 102 to the corresponding switching elements
105. Similarly, M scanning lines 107 are used for connecting respective output terminals
G(j) (j = 1,2, ...,M) of the scanning driver 103 to the corresponding switching elements
105. As the switching elements 105, thin film transistors (TFTs) can be used. Alternatively,
other types of switching elements may also be used. The data line may be called "a
source line" or "a column line". The scanning line may be called "a gate line" or
"a row line".
[0038] The scanning driver 103 sequentially outputs a voltage which is kept at a high level
during a specific time period from its output terminals G(j) to the corresponding
scanning lines 107. The specific time period is referred to as one horizontal period
jH (where j is an integer of 1 to M). The total length of time obtained by adding
up all the horizontal periods jH (i.e., 1 H + 2H + 3H + ... + MH), a blanking period
and a vertical synchronizing period is referred to as one vertical period.
[0039] When the level of the voltage which is output from the output terminal G(j) of the
scanning driver 103 to the scanning line 107 is high, the switching element 105 connected
to the output terminal G(j) is in the ON-state. When the switching element 105 is
in the ON-state, the pixel 104 connected to the switching element 105 is charged in
accordance with the voltage which is output from the output terminal S(j) of the data
driver 102 to the corresponding data line 106. The voltage of the thus charged pixel
104 remains unchanged for about one vertical period until it is charged again by the
subsequent voltage to be supplied from the data driver 102.
[0040] Figure 2 shows the relationship among digital video data DA, sampling pulses T
smpi, and an output pulse signal OE, during the jth horizontal period jH determined by
a horizontal synchronizing signal H
sy
n. As can be seen from Figure
2, while sampling pulses T
smp1, T
smp2, ..., T
smpi, ..., and T
smpN are sequentially applied to the data driver 102, digital video data DA
1, DA
2 ..., DA ..., and DA
N are fed into the data driver 102 accordingly. The jth output pulse OE
j determined by the output pulse signal OE is then applied to the data driver 102.
On receiving the jth output pulse OE
j, the data driver 102 outputs voltages from its output terminals S(i) to the corresponding
data lines 106.
[0041] Figure 3 shows the relationship among the horizontal synchronizing signal H
sy
n, the digital video data DA, the output pulse signal OE, and the timing of outputs
of the data driver 102 and scanning driver 103, during one vertical period determined
by a vertical synchronizing signal V
sy
n. In Figure 3, a SOURCE(j) indicates a level range of voltages output from the data
driver 102, with such timing as shown in Figure 2 and in accordance with the digital
video data applied during the horizontal period jH. The SOURCE(j) is shown as a hatched
rectangular area to indicate a level range of voltages output from all the N output
terminals S(1) to S(N) of the data driver 102. While the voltages indicated by the
SOURCE(j) are applied to the data lines 106, the voltage which is outputfrom the jth
outputterminal G(j) of the scanning driver 103 to the jth scanning line 107 is changed
to and kept at a high level, thereby turning on all the N switching elements 105 connected
to the jth scanning line 107. As a result, the N pixels 104 respectively connected
to these N switching elements 105 are charged in accordance with the voltage applied
to the corresponding data lines 106 from the data driver 102.
[0042] The above-described process is repeated M times, i.e., for the 1st to Mth scanning
lines 107, so that an image corresponding to one vertical period is displayed. In
the case of non-interlace type display apparatus, the produced image serves as a complete
display image on the display screen thereof.
[0043] In this specification, the time interval between the jth output pulse OE
j and the (j+1)th output pulse OE
j+1 in the output pulse signal OE is defined as "one output period". This means that
one output period is equal to a period represented by SOURCE(j) shown in Figure 3.
In cases where usual line sequential scanning is performed, it is preferable that
one output period is made equal to one horizontal period. The reason for this is as
follows. While the data driver 102 outputs voltages corresponding to digital video
data for one horizontal (scanning) line, to the data lines 106, it also performs sampling
of digital video data for the next horizontal line. The maximum allowable length of
time during which these voltages can be output from the data driver 102 is equal to
one horizontal period. Furthermore, except for special cases, as the output period
becomes longer, the pixels can be charged more accurately. In the driving circuit
described herein, therefore, one output period is equal to one horizontal period.
According to the present invention, however, one output period is not necessarily
required to be equal to one horizontal period.
[0044] Figure 4 shows, in addition to the timings of the respective signals shown in Figures
2 and 3, the levels of voltages which are applied to the pixels P(j, i) (j = 1, 2,
..., M) in accordance with the timings.
[0045] Figure 5 shows an exemplary waveform for a voltage signal output from the data driver
102 to the data lines 106 in one output period. In the case of the conventional data
driver, the voltage level of the voltage signal output to the data lines 106 is constant
during one output period. On the other hand, from the data driver 102 in this example
according to the invention, the voltage signal output to the data lines 106 includes
an oscillating component which oscillates during one output period. As is shown in
Figure 5, the voltage signal is a pulse- like signal, and a ratio of a high-level
period to a low-level period, i.e., a duty ratio n:m is selected as described below.
[0046] Figure 6 shows a configuration of a part of the data driver 102 in the driving circuit
101. The circuit 60 shown in Figure 6 outputs a video signal from an nth output terminal
S(n) to one data line 106. The data driver 102 includes circuits 60 the number of
which is equal to the number of the data lines 106 provided in the display section
100. Herein, it is assumed that the video data consists of 6 bits (Do, D
1, D
2, D
3, D
4, D
5). On such an assumption, the video data may have 64 kinds of values of 0 - 63, and
a signal voltage applied to each pixel is one of nine gray-scale voltages Vo, V
8, V
16, V
24, V
32, V
40, V
48, V
56, and V64, and interpolated voltages which are produced from any pair of the gray-scale
voltages chosen from V
o, V
8, V
16, V
24, V
32, V
40, V
48, V
56, and V
64
[0047] The circuit 60 includes a sampling flip-flop M
SMP which performs the sampling operation, a holding flip-flop M
H which performs the holding operation, a selection control circuit SCOL, and analog
switches ASW
o-ASW
8. To each of the analog switches ASW
0-ASW
8, a corresponding one of nine gray-scale voltages V
o, V
8, V
16, V
24, V
32, V
40, V
48, V
56, and V
64 is supplied. The gray-scale voltages V
0-V
64 have respective levels which are different from each other. The selection control
circuit SCOL is provided with seven oscillating signals t
1- t
7. The oscillating signals t
1-t
7 have respective duty ratios which are different from each other.
[0048] As the sampling flip-flop M
SMP and the holding flip-flop M
H, for example, D-type flip-flops can be used. It is appreciated that such sampling
and holding flip-flops can be realized by using other types of circuit elements.
[0049] Next, by referring to Figure 6, the operation of the circuit 60 is described. At
the rising of a sampling pulse T
SMPn corresponding to the nth pixel, the sampling flip-flop M
SMP gets video data (Do, D
1, D
2, D
3, D
4, D
5), and holds the video data therein. When such video data sampling for one horizontal
period is completed, an output pulse signal OE is applied to the holding flip-flop
M
H. When the output pulse signal OE is applied, the video data held in the sampling
flip-flop M
SMP is fed into the holding flip-flop M
H and output to the selection control circuit SCOL. The selection control circuit SCOL
receives the video data, and produces a plurality of control signals in accordance
with the value of the video data. The control signals are used for switching the ON/OFF
states of the respective analog switches ASW
0-ASW
8. The video data input to the selection control circuit SCOL is represented by do,
d
1, d
2, d
3, d
4, and d
5, and the control signals output from the selection control circuit SCOL are represented
by So, S
8, S
16, S
24, S
32, S
40, S
48, S
56, and S64.
[0050] Table 2 is a logical table for the lower three bits d
2,d
1, and do of the 6-bit video data. The 1 st to 3rd columns of Table 2 indicate the
values of video data bits d
2, d
1, and do, respectively. The 4th to 11th columns of Table 2 indicate which oscillating
signal is specified from the oscillating signals to-t
7. In the 4th to 11th columns of Table 2, the oscillating signal which is indicated
by a value of 1 is specified. For example, in the case of (d
2, d
1, do) =(0, 0, 0), the oscillating signal to is specified. In this example, the oscillating
signals to-t
7 are clock signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7,
respectively. Herein, if an oscillating signal has a duty ratio of k:0 or 0:k (k is
a natural number), the oscillating signal is defined as always being at a fixed level.
The oscillating signals t
5, t
8, and t
7 are the signals obtained by inverting the oscillating signals t
3, t
2, and t
1.

[0051] From the logical table of Table 2, the following logical equation is obtained.

[0052] In the above equation, (i) indicates a value of binary data (d
2, d
1, do) which is represented in a decimal notation. That is, (0) = (d
2, d
1, do) (0, 0, 0), (1) = (d
2, d
1, do) = (0, 0, 1), (2) = (d
2, d
1, do) (0, 1, 0), (3) = (d
2, d
1, do) = (0, 1, 1), (4) = (d
2, d
1, do) =(1,0, 0), (5) = (d
2, d
1, do) = (1, 0, 1), (6) = (d
2, d
1, do) = (1, 1, 0), and (7) = (d
2, d
1, do) =(1, 1, 1).
[0053] The oscillating signal to is continually at a level of "1", so that Equation (6)
can alternatively be represented as the following equation.

[0054] Table 3 is a logical table representing the relationships among the upper three bits
d
5, d
4, and d
3 of the 6- bit video data, and the control signals So, S
8, S
16, S
24, S
32, S
40, S
48,_S
56, and S
64. In Table 3, a variable T denotes a signal T which is defined by Equations (6) and
(7). A variable T denotes an inverted signal T obtained by inverting the signal T.

[0056] In the above equations, [i] indicates a value of binary data (d
5, d
4, d
3), where i = (8 x j), and j is a value of binary data (d
5, d
4, d
3) which is represented in a decimal notation. For example, [8] = (d
5, d
4, d
3) = (0, 0, 1). In addition, "T" denotes an inverted signal of the signal T.
[0057] In accordance with the respective logical equations which are described above, logical
circuits 70, 80, 90, and 95 shown in Figures 7 through 10 are obtained. The selection
control circuit SCOL is constructed, for example, by the logical circuits 70, 80,
90, and 95 shown in Figures 7 through 10.
[0058] The logical circuit 70 shown in Figure 7 selectively outputs oscillating signal specifying
signals (0)-(7) for specifying one of a plurality of oscillating signals to-t
7, in accordance with the lower 3 bits d
2, d
1, and do of the video data. More specifically, the video data d
2, d
1, and do and the inverted signals which are respectively obtained by inverting the
video data d
2, d
1, and do by inverter circuits INV
0 and INV
2 are input into AND circuits AG
0-AG
7 in such combinations that constitute 0-7 in binary notation. The oscillating signal
specifying signals (0)-(7) are thus obtained as the outputs of the AND circuits AGo-
AG
7.
[0059] The logical circuit 80 shown in Figure 8 specifies one of the plurality of oscillating
signals to-t
7 in accordance with the oscillating signal specifying signals, and produces the specified
oscillating signal T and the inverted oscillating signal T which is obtained by inverting
the specified oscillating signal T by an inverter circuit INV
3. More specifically, the oscillating signal specifying signals (1)-(7) and the oscillating
signals t
1-t
7 are input into AND circuits BG
1-BG
7, respectively, as is shown in Figure 8. The oscillating signal specifying signal
(0) and the outputs of the AND circuits BG
1-BG
7 are supplied to an OR circuit CG. The oscillating signal T and the inverted oscillating
signal T are obtained as the output of the OR circuit CG.
[0060] The logical circuit 90 shown in Figure 9 selectively outputs gray-scale voltage specifying
signals [0], [8], [16], [24], [32], [40], [48], and [56] for specifying a pair of
gray-scale voltages from among a plurality of gray-scale voltages, in accordance with
the upper three bits d
5, d
4, and d
3 of the video data. More specifically, the video data d
5, d
4, and d
3 and the inverted signals which are respectively obtained by inverting the video data
d
5, d
4, and d
3 by inverter circuits INV
4-INV
6 are input to AND circuits DG
0-DG
7 in such combinations which constitute 0-7 in the binary notation. As the outputs
of the AND circuits DG
0-DG
7, the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48],
and (56] are obtained.
[0061] The logical circuit 95 shown in Figure 10 selectively outputs the control signals
S
0-S
64, in accordance with the gray-scale voltage specifying signals [0], [8], [16], [24],
[32], [40], [48], and [56], the oscillating signal T, and the inverted oscillating
signal T. More specifically, the gray-scale voltage specifying signals [0], [8], [16],
[0062] [24], [32], [40], [48], and [56], and the oscillating signal T are input into AND
circuits EG
o, EG
2, EG
4, EG
6, EG
s, EG
1o, EG
12, and EG
14, respectively. The gray-scale voltage specifying signals [0], [8], [16], [24], [32],
[40], [48], and [56] and the inverted oscillating signal T are input into AND circuits
EG
1, EG
3, EG
s, EG
7, EGg, EG
11, EG
13, and EG
15, respectively. The outputs of the AND circuits EG
1 and EG
2 are coupled to the inputs of an OR circuit FG
1, respectively. The outputs of the AND circuits EG
3 and EG
4 are coupled to the inputs of an OR circuit FG
2, respectively. The outputs of the AND circuits EG
5 and EG
6 are coupled to an OR circuit FG
3, respectively. The outputs of the AND circuits EG
7 and EG
8 are coupled to the inputs of an OR circuit FG
4, respectively. The outputs of the AND circuits EG
9 and EG
10 are coupled to the inputs of an OR circuit FG
s, respectively. The outputs of the AND circuits EG
11 and EG
12 are coupled to the inputs of an OR circuit FG
6, respectively. The outputs of the AND circuits EG
13 and EG
14 are coupled to the inputs of an OR circuit FG
7, respectively. As the outputs of the AND circuit EG
o, the OR circuits FG
1-FG
7, and the AND circuit EG
15, the control signals So, S
8, S
16, S
24, S
32, S
40, S
48, S
56 and S
64 are obtained.
[0063] The control signals So, S
8, S
16, S
24, S
32, S
40, S
48, S
56, and S
64 are supplied to the corresponding analog switches ASW
0-ASW
8. Each of the control signals So,
S8,
S16, S
24, S
32, S
40, S
48, S
56, and S
64 has either a high-level value or a low-level value. For example, if the control signal
is at a high level, the corresponding analog switch is controlled to be in the ON-state.
If the control signal is at a low level, the corresponding analog switch is controlled
to be in the OFF-state. Alternatively, the relationship between the level of the control
signal and the ON/OFF state of the analog signal can be set in a reverse manner.
[0064] As described above, in the case where video data consists of a plurality of bits,
a waveform of an oscillating voltage is specified in accordance with video data consisting
of at least one bit selected from the plurality of bits. Then, in accordance with
video data consisting of bits other than the above selected bit(s), a pair of gray-scale
voltages are specified from a plurality of gray-scale voltages. As a result, a voltage
signal of an appropriate level can be output for every value of video data. The oscillating
voltage is used for realizing a plurality of interpolated gray-scale voltages between
the specified pair of gray-scale voltages which are specified from among the plurality
of gray-scale voltages. In the case where the value of the video data is a multiple
of 8, only one of the plurality of gray-scale voltages may be output. In such a case,
the duty ratio n:m of the oscillating signal or the control signal is interpreted
to be k:0 or 0:k (k is a natural number). Alternatively, regardless of whether the
value of the video data is a multiple of 8 or not, the specified pair of gray-scale
voltages among the plurality of gray-scale voltages may be alternately output. As
described above, the selection control circuit SCOL according to the invention constructed
of the logical circuits 70, 80, 90, and 95 shown in Figures 7 through 10 has a simplified
construction as compared with the conventional selection control circuit SCOL shown
in Figure 12 which is constructed of the logical circuits shown in Figures 14 and
15. According to the invention, it is possible to display an image with multiple gray
scales, such as 64 gray scales, by using a driving circuit having a more simplified
construction. For example, in order to realize a display image with 64 gray scales,
only 9 kinds of gray-scale voltages are required. The actual data driver requires
selection control circuits SCOL the number of which is equal to the number of data
lines. Thus, the circuit scale of the selection control circuits SCOL largely affects
the chip size of an integrated circuit (LSI) on which a data driver is installed.
According to the invention, it is possible to significantly reduce the size of the
integrated circuit including the selection control circuits SCOL. As a result, the
production cost of the integrated circuit can be reduced. In cases where the number
of bits of video data is increased in order to realize an image with a larger number
of gray scales, such miniaturization of the circuit scale of the data driver is of
great use. Accordingly, it is possible to make further progress in the size and cost
reduction of the integrated circuit. According to the invention, it is possible to
obtain one or more interpolated voltages from voltages supplied from given voltage
sources, whereby the number of voltage sources can be greatly decreased as compared
with a conventional driving circuit which requires a large number of voltage sources.
If the voltage sources are provided from the outside of the driving circuit, the number
of input terminals of the driving circuit can be reduced. If the driving circuit is
constructed as an LSI, the number of input terminals of the LSI can be reduced. According
to the invention, it is possible to realize a driving LSI for displaying an image
with multiple gray scales which could not be realized by the prior art example because
of the increase in the number of terminals. In the present invention, the following
effects can be attained: (1) the production cost of a display apparatus and a driving
circuit are largely reduced; (2) a driving circuit for multiple gray scales which
could not be practically produced due to the chip size or the LSI installation can
be readily produced; and (3) the power consumption is decreased because a large number
of voltage sources are not required. Various other modifications will be apparent
to and can be readily made by those skilled in the art without departing from the
scope and spirit of this invention. Accordingly, it is not intended that the scope
of the claims appended hereto be limited to the description as set forth herein, but
rather that the claims be broadly construed.