The present invention relates to a driving circuit for a display apparatus. More particularly, the present invention relates to a driving circuit for an active matrix type liquid crystal display apparatus which displays an image with multiple gray scales in accordance with digital video signals.

An active matrix type liquid crystal display apparatus includes a display panel and a driving circuit for driving the display panel. The display panel includes a pair of glass substrates and a liquid crystal layer formed between the pair of glass substrates. On one of the pair of glass substrates, a plurality of gate lines and a plurality of data lines are formed. The driving circuit is disposed for every pixel in the display panel, and the driving circuit applies a driving voltage to the liquid crystal of the display panel. The driving circuit includes a gate driver for individually selecting one of a plurality of switching elements connected to the gate lines and the data lines, and a data driver for supplying a video signal corresponding to an image to pixel electrodes via the selected switching element.

Figure 11 shows a configuration of a part of a data driver in a prior art driving circuit. The circuit 110 shown in Figure 11 outputs a video signal to one of a plurality of data lines. Accordingly, the data driver requires circuits 110 the number of which is equal to the number of data lines provided in a display panel. For simplicity of explanation, it is herein assumed that video data consists of three bits (D₀, D₁, D₂). On such an assumption, the video data may have eight values of 0 to 7, and a signal voltage supplied to each pixel is one of eight levels V₀-V₇.

The circuit 110 includes a sampling flip-flop M_SMP, a holding flip-flop M_H, a decoder DEC, and analog switches ASW₀-ASW₇. To each of the analog switches ASW₀-ASW₇, a corresponding one of external source voltages V₀-V₇ of respective eight levels which are different from each other is supplied. In addition, to the analog switches ASW₀-ASW₇, control signals S₀-S₇ are supplied from the decoder DEC, respectively. Each of the control signals S₀-S₇ is used for switching the ON/OFF state of the respective analog switch.

Next, the operation of the circuit 110 is described. At the rising of a sampling pulse T_SMPn corresponding to the nth pixel, the sampling flip-flop M_SMP gets video data (D₀, D₁, D₂), and holds the video data therein. When such video data sampling for one horizontal period is completed, an output pulse signal OE is applied to the holding flip-flop M_H. Upon receiving the output pulse signal OE, the holding flip-flop M_H gets the video data (D₀, D₁, D₂) from the sampling flip-flop M_SMP, and transfers the video data to the decoder DEC.

The decoder DEC decodes the video data (D₀, D₁, D₂), and produces a control signal for turning on one of the analog switches ASW₀-ASW₇ in accordance with the respective values (0-7) of the video data (D₀, D₁, D₂). As a result, one of the external source voltages V₀-V₇ is output to a data line O_n. For example, in the case where the value of the video data held in the holding flip-flop M_H is 3, the decoder DEC outputs a control signal S₃ which turns on the analog switch ASW₃. As a result, the analog switch ASW₃ becomes into the ON-state, and V₃ of the external source voltages V₀-V₇ is output to the data line O_n.

Such a prior art data driver involves a problem in that, as the number of bits in video data increases, the circuit configuration becomes complicated and the size of the circuit is increased. This is because the prior art data driver requires gray-scale voltages the number of which is equal to the gray scales to be displayed. For example, in the case where the video data consists of 4 bits for displaying 16 gray-scale images, the number of required gray-scale voltages is: 2⁴ = 16. Similarly, in the case where the video data consists of 6 bits for displaying 64 gray-scale images, the number of required gray-scale voltages is: 2⁶ = 64. In the case of 8-bit video data for displaying 256 gray-scale images, the number of required gray-scale voltages is: 2⁸ = 256. As described above, the prior art data driver requires a large number of gray-scale voltages as the number of bits of video data increases. This causes the circuit configuration to be complicated and the circuit size to be increased. Moreover, interconnections between voltage source circuits and analog switches are also complicated.

For the above-mentioned reasons, the actual application of such a prior art data driver is limited to 3-bit video data or 4-bit video data.

In order to solve such prior art problems, there have been proposed methods and circuits for driving a display apparatus in Japanese Laid-Open Patent Publication Nos. 4-136983, 4-140787 corresponding to EP-A-0 478 386, and 6-27900 corresponding to EP-A-0 515 191.

Figure 12 shows a configuration for a part of a driving circuit disclosed in Japanese Laid-Open Patent Publication No. 6-27900. The circuit 120 shown in Figure 12 outputs a video signal to one of a plurality of data lines. Accordingly, the data driver requires circuits 120 the number of which is equal to the number of data lines provided in a display panel. It is herein assumed that video data consists of 6 bits (D₀, D₁, D₂, D₃, D₄, D₅). On such an assumption, the video data may have 64 values of 0-63, and a signal voltage applied to each pixel is one of nine gray-scale voltages V₀, V₈, V₁₆, V₂₄, V₃₂, V₄₀, V₄₈, V₅₆, and V₆₄, and a plurality of interpolated voltages which are produced from the gray-scale voltages V₀, V₈, V₁₆, V₂₄, V₃₂, V₄₀, V₄₈, V₅₆, and V₆₄.

The circuit 120 includes a sampling flip-flop M_SMP, a holding flip-flop M_H, a selection control circuit SCOL, and analog switches ASW₀-ASW₈. To each of the analog switches ASW₀-ASW₈, is applied a corresponding one of gray-scale voltages V₀, V₈, V₁₆, V₂₄, V₃₂, V₄₀, V₄₈, V₅₆, and V₆₄ of respective levels which are different from each other. To the analog switches ASW₀-ASW₈, control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄ are supplied from the selection control circuit SCOL, respectively. Each of the control signals are used to switch the ON/OFF state of the analog signal.

To the selection control circuit SCOL, clock signals t₁, t₂, t₃, and t₄ are supplied. As is shown in Figure 13, the clock signals t₁, t₂, t₃, and t₄ have duty ratios which are different from each other. The selection control circuit SCOL receives 6-bit video data d₅, d₄, d₃, d₂, d₁, and d₀, and outputs one of control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄ in accordance with the value of the received video data. The relationship between the input and the output of the selection control circuit SCOL is determined by using a logical table.

Table 1 shows a logical table for the selection control circuit SCOL. The 1st to 6th columns of Table 1 indicate values of bits d₅, d₄, d₃, d₂, d₁, and d₀ of the video data, respectively. The 7th to 15th columns of Table 1 indicate values of control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄, respectively. Each blank in the 7th to 15th columns in Table 1 means that the value of the control signal is 0. In addition, "t_i" indicates that the value of the control signal is 1 when the value of the clock signal t_i is 1, and the value of the control signal is 0 when the value of the clock signal t_i is 0. Also, "$\overline{{\text{t}}_{\text{i}}}$" indicates that the value of the control signal is 0 when the value of the clock signal t_i is 1, and the value of the control signal is 1 when the value of the clock signal t_i is 0. Herein, i = 1, 2, 3, and 4.

As is seen from Table 1, when the value of the video data is a multiple of 8, one of the gray-scale voltages V₀, ..., V₆₄ is output to the data line O_n. When the value of the video data is not a multiple of 8, an oscillating voltage which oscillates between a pair of gray-scale voltages V₀, ..., V₆₄ at a duty ratio of one of the clock signals t₁, t₂, t₃, and t₄ is output to the data line O_n. The data driver 120 produces seven different oscillating voltages between respective adjacent gray-scale voltages, in accordance with the logical table of Table 1. Thus, it is possible to attain 64 gray-scale images by using only 9 levels of gray-scale voltages.

The following equations are logical equations which define the relationships among the video data d₅, d₄, d₃, d₂, d₁, and d₀, the clock signals t₁, t₂, t₃, and t₄, and the control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄ shown in Table 1.$$\begin{gathered} {\text{S}}_{\text{0}}{\text{= {0} + {1}t}}_{\text{1}}{\text{+ {2}t}}_{\text{2}}{\text{+ {3}t}}_{\text{3}}{\text{+ {4}t}}_{\text{4}}{\text{+ {5}"t}}_{\text{3}}\text{" +} \\ {\text{{6}"t}}_{\text{2}}{\text{" + {7}"t}}_{\text{1}}\text{"} \end{gathered}$$$$\begin{gathered} {\text{S}}_{\text{8}}{\text{= {1}"t}}_{\text{1}}{\text{+ {2}"t}}_{\text{2}}{\text{" + {3}"t}}_{\text{3}}{\text{" + {4}"t}}_{\text{4}}{\text{" + {5}t}}_{\text{3}}\text{+} \\ {\text{{6}t}}_{\text{2}}{\text{+ {7}t}}_{\text{1}}{\text{+ {8} + {9}t}}_{\text{1}}{\text{+ {10}t}}_{\text{2}}{\text{+ {11}t}}_{\text{3}}\text{+} \\ {\text{{12}t}}_{\text{4}}{\text{+ {13}"t}}_{\text{3}}{\text{" + {14}"t}}_{\text{2}}{\text{" + {15}"t}}_{\text{1}}\text{"} \end{gathered}$$$$\begin{gathered} {\text{S}}_{\text{16}}{\text{= {9}"t}}_{\text{1}}{\text{+ {10}"t}}_{\text{2}}{\text{" + {11}"t}}_{\text{3}}{\text{" + {12}"t}}_{\text{4}}{\text{" + {13}t}}_{\text{3}} \\ {\text{+ {14}t}}_{\text{2}}{\text{+ {15}t}}_{\text{1}}{\text{+ {16} + {17}t}}_{\text{1}}{\text{+ {18}t}}_{\text{2}} \\ {\text{+ {19}t}}_{\text{3}}{\text{+ {20}t}}_{\text{4}}{\text{+ {21}"t}}_{\text{3}}{\text{" + {22}"t}}_{\text{2}}{\text{" + {23}"t}}_{\text{1}}\text{"} \end{gathered}$$

Similarly, the control signals S₂₄, S₃₂, S₄₀, and S₄₈ are defined. The control signals S₅₆ and S₆₄ are defined as follows.$$\begin{gathered} {\text{S}}_{\text{56}}{\text{= {49}"t}}_{\text{1}}{\text{" + {50}"t}}_{\text{2}}{\text{" + {51}"t}}_{\text{3}}{\text{" + {52}"t}}_{\text{4}}\text{"} \\ {\text{+ {53}t}}_{\text{3}}{\text{+ {54}t}}_{\text{2}}{\text{+ {55}t}}_{\text{5}}{\text{+ {56} + {57}t}}_{\text{1}} \\ {\text{+ {58}t}}_{\text{2}}{\text{+ {59}t}}_{\text{3}}{\text{+ {60}t}}_{\text{4}}{\text{+ {61}"t}}_{\text{3}}{\text{" + {62}"t}}_{\text{2}}\text{"} \\ {\text{+ {63}"t}}_{\text{1}}\text{"} \end{gathered}$$$$\begin{gathered} {\text{S}}_{\text{64}}{\text{= {57}"t}}_{\text{1}}{\text{" + {58}"t}}_{\text{2}}{\text{" + {59}"t}}_{\text{3}}{\text{" + {60}"t}}_{\text{4}}\text{"} \\ {\text{+ {61}t}}_{\text{3}}{\text{+ {62}t}}_{\text{2}}{\text{+ {63}t}}_{\text{1}} \end{gathered}$$

In the above equations, {i} indicates a value when the binary data (d₅, d₄, d₃, d₂, d₁, d₀) is represented in the decimal notation. For example, {1} = (d₅, d₄, d₃, d₂, d₁, d₀) = (0, 0, 0, 0, 0, 1). In addition, "t_i" indicates a signal which is inverted from the signal t_i.

On the basis of the above logical equations, logical circuits shown in Figures 14 and 15 are obtained. The selection control circuit SCOL is constructed by the logical circuits shown in Figures 14 and 15.

The logical circuit shown in Figure 14 produces 64 kinds of gray-scale selection data {0} - {63} in accordance with the value of 6-bit video data (d₅, d₄, d₃, d₂, d₁, d₀). The logical circuit shown in Figure 15 produces control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄, based on the gray-scale selection data {0} - {63} and the clock signals t₁, t₂, t₃, and t₄. For example, a case where the video data (d₅, d₄, d₃, d₂, d₁, d₀) = (0, 0, 0, 0, 0, 1) is input to the selection control circuit SCOL is explained. In such a case, the logical circuit shown in Figure 14 outputs the gray-scale selection data (1). The logical circuit shown in Figure 15 receives the gray-scale selection data (1) and alternately outputs the control signal S₀ and the control signal S₈ at a duty ratio of the clock signal t₁. As a result, the gray-scale voltage V₀ and the gray-scale voltage V₈ are alternately output via the analog switch ASW₀ and the analog switch ASW₁ at the duty ratio of the clock signal t₁ to the data line O_n.

The actual data driver requires the selection control circuits SCOL the number of which is equal to the number of data lines. Thus, the circuit scale of the selection control circuit SCOL largely affects the chip size of the integrated circuit on which the data driver is installed. If the circuit scale of the selection control circuit SCOL becomes large, the cost for the integrated circuit is increased. Moreover, if the number of bits of video data increases in order to realize an image with a larger number of gray scales, the circuit scale of the data driver is further increased. This also increases the size and the production cost of the integrated circuit.

The present invention provides a driving circuit for driving a display apparatus, the display apparatus including pixels and data lines for applying voltages to said pixels and displaying, in use, an image with multiple grey scales in accordance with video data consisting of a plurality of bits, said driving circuit comprising:

• oscillating voltage selecting means for selecting one of a plurality of oscillating signals oscillating between first and second predetermined levels and having respective duty ratios which are different from each other in accordance with video data consisting of bits selected from said plurality of bits, and for outputting said selected oscillating signal and an inverted oscillating signal which is obtained by inverting said selected oscillating signal;
• grey-scale voltage selecting means for producing grey-scale voltage selecting signals which select a first grey-scale voltage and a second grey-scale voltage from a plurality of grey-scale voltages supplied by a grey-scale voltage supply means, in accordance with video data consisting of bits other than said selected bits of said plurality of bits; and
• output means for outputting said first grey-scale voltage and said second grey-scale voltage selected by said grey-scale voltage selecting means to said data lines, in accordance with said oscillating signal and said inverted oscillating signal, the output means outputting the first grey scale voltage when the oscillating signal is at said first predetermined level and the second selected grey scale voltage when the inverted oscillating signal is at said first predetermined level.

In a preferred embodiment, the first grey-scale voltage and said second grey-scale voltage are adjacent ones of said plurality of grey-scale voltages.

In a preferred embodiment, the plurality of oscillating signals include oscillating signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7, respectively.

In a preferred embodiment, the output means comprises

• (a) control signal output means for outputting a first control signal which oscillates at substantially the same duty ratio as that of said oscillating signal to one of said switching means which is supplied with said first grey-scale voltage selected by said grey-scale voltage selecting signals and for outputting a second control signal which oscillates at substantially the same duty ratio as that of said inverted oscillating signal to one of said switching means which is supplied with said second grey-scale voltage selected by said grey-scale voltage selecting signals; and
• (b) a plurality of switching means, each of said plurality of switching means being supplied with a corresponding one of said plurality of control signals and a corresponding one of the plurality of grey-scale voltages, said grey-scale voltage supplied to said switching means being output to said data lines via said switching means in accordance with said control signal.

In a preferred embodiment, the switching means is an analogue switch.

According to the driving circuit of the invention, a pair of gray-scale voltages are selected (specified) among a plurality of gray-scale voltages, and one of a plurality of oscillating signals is specified. The driving circuit outputs a voltage signal which oscillates between the specified pair of gray-scale voltages at the oscillating frequency of the specified oscillating signal. Therefore, a plurality of interpolated gray scales can be realized between a plurality of applied gray-scale voltages.

According to the driving circuit of the invention, by using the gray-scale voltage specifying means and the oscillating signal specifying means, it is possible to always realize an image display with multiple gray scales in both cases where the driving circuit directly outputs one of the plurality of gray-scale voltages and where the driving circuit alternately outputs the specified pair of gray-scale voltages.

Accordingly, it is unnecessary to provide an additional driving circuit depending on the cases where the driving circuit directly outputs one of the plurality of gray-scale voltages and where the driving circuit alternately outputs the specified pair of gray-scale voltages. As a result, it is possible to simplify the configuration of the driving circuit, and the size of the driving circuit can be minimized.

Thus, the invention described herein makes possible the advantage of providing a driving circuit for a display apparatus, which has a simplified and small construction, and which can display an image with multiple gray scales in accordance with multi-bit video data.

This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.

Figure 1 is a diagram showing a construction of a liquid crystal display apparatus.

Figure 2 is a timing chart illustrating the relationship among input data, sampling pulses, and an output pulse in one horizontal period.

Figure 3 is a timing chart illustrating the relationship among input data, an output pulse, an output voltage, and a gate pulse in one vertical period.

Figure 4 is a timing chart illustrating the relationship among input data, an output pulse, an output voltage, a gate pulse, and a voltage applied to a pixel in one vertical period.

Figure 5 shows waveforms of an output voltage oscillating in one output period.

Figure 6 is a diagram showing a part of a configuration for a data driver in a driving circuit in an example according to the invention.

Figure 7 is a diagram showing a part of a configuration of a selection control circuit SCOL in the driving circuit in the example according to the invention.

Figure 8 is a diagram showing another part of the configuration of the selection control circuit SCOL in the driving circuit in the example according to the invention.

Figure 9 is a diagram showing another part of the configuration of the selection control circuit SCOL in the driving circuit in the example according to the invention.

Figure 10 is a diagram showing another part of the configuration of the selection control circuit SCOL in the driving circuit in the example according to the invention.

Figure 11 is a diagram showing a part of a configuration for a data driver in a conventional driving circuit.

Figure 12 is a diagram showing a part of a configuration of a data driver in a driving circuit of a related art.

Figure 13 shows waveforms of signals t₁-t₄ supplied to a selection control circuit SCOL.

Figure 14 is a diagram showing a part of a configuration of a selection control circuit SCOL in the conventional driving circuit.

Figure 15 is a diagram showing another part of the configuration of a selection control circuit SCOL in the conventional driving circuit.

Hereinafter, the present invention will be described by way of illustrative examples in accordance with the accompanying drawings. In the following description, a matrix type liquid crystal display apparatus is used as an example of a display apparatus. It is appreciated that the present invention is applicable to other types of display apparatus.

Figure 1 shows a construction of a matrix type liquid crystal display apparatus. The liquid crystal display apparatus shown in Figure 1 includes a display section 100 for displaying a video image, and a driving circuit 101 for driving the display section 100. The driving circuit 101 includes a data driver 102 which provides video signals to the display section 100 and a scanning driver 103 which provides scanning signals to the display section 100. The data driver may be called "a source driver" or "a column driver". The scanning driver may be called "a gate driver" or "a row driver".

The display section 100 includes an M x N array of pixels 104 (M pixels in each column and N pixels in each row; where M and N are positive integers), and also includes switching elements 105 respectively connected to the pixels 104.

In Figure 1, N data lines 106 are used for connecting respective output terminals S(i) (i = 1, 2, ...,N) of the data driver 102 to the corresponding switching elements 105. Similarly, M scanning lines 107 are used for connecting respective output terminals G(j) (j = 1, 2, ...,M) of the scanning driver 103 to the corresponding switching elements 105. As the switching elements 105, thin film transistors (TFTs) can be used. Alternatively, other types of switching elements may also be used. The data line may be called "a source line" or "a column line". The scanning line may be called "a gate line" or "a row line".

The scanning driver 103 sequentially outputs a voltage which is kept at a high level during a specific time period from its output terminals G(j) to the corresponding scanning lines 107. The specific time period is referred to as one horizontal period jH (where j is an integer of 1 to M). The total length of time obtained by adding up all the horizontal periods jH (i.e., 1H + 2H + 3H + ... + MH), a blanking period and a vertical synchronizing period is referred to as one vertical period.

When the level of the voltage which is output from the output terminal G(j) of the scanning driver 103 to the scanning line 107 is high, the switching element 105 connected to the output terminal G(j) is in the ON-state. When the switching element 105 is in the ON-state, the pixel 104 connected to the switching element 105 is charged in accordance with the voltage which is output from the output terminal S(j) of the data driver 102 to the corresponding data line 106. The voltage of the thus charged pixel 104 remains unchanged for about one vertical period until it is charged again by the subsequent voltage to be supplied from the data driver 102.

Figure 2 shows the relationship among digital video data DA, sampling pulses T_smpi, and an output pulse signal OE, during the jth horizontal period jH determined by a horizontal synchronizing signal H_syn. As can be seen from Figure 2, while sampling pulses T_smp1, T_smp2, ..., T_smpi, ..., and T_smpN are sequentially applied to the data driver 102, digital video data DA₁, DA₂ ..., DA_i ..., and DA_N are fed into the data driver 102 accordingly. The jth output pulse OE_j determined by the output pulse signal OE is then applied to the data driver 102. On receiving the jth output pulse OE_j, the data driver 102 outputs voltages from its output terminals S(i) to the corresponding data lines 106.

Figure 3 shows the relationship among the horizontal synchronizing signal H_syn, the digital video data DA, the output pulse signal OE, and the timing of outputs of the data driver 102 and scanning driver 103, during one vertical period determined by a vertical synchronizing signal V_syn. In Figure 3, a SOURCE(j) indicates a level range of voltages output from the data driver 102, with such timing as shown in Figure 2 and in accordance with the digital video data applied during the horizontal period jH. The SOURCE(j) is shown as a hatched rectangular area to indicate a level range of voltages output from all the N output terminals S(1) to S(N) of the data driver 102. While the voltages indicated by the SOURCE(j) are applied to the data lines 106, the voltage which is output from the jth output terminal G(j) of the scanning driver 103 to the jth scanning line 107 is changed to and kept at a high level, thereby turning on all the N switching elements 105 connected to the jth scanning line 107. As a result, the N pixels 104 respectively connected to these N switching elements 105 are charged in accordance with the voltage applied to the corresponding data lines 106 from the data driver 102.

The above-described process is repeated M times, i.e., for the 1st to Mth scanning lines 107, so that an image corresponding to one vertical period is displayed. In the case of non-interlace type display apparatus, the produced image serves as a complete display image on the display screen thereof.

In this specification, the time interval between the jth output pulse OE_j and the (j+1)th output pulse OE_j+1 in the output pulse signal OE is defined as "one output period". This means that one output period is equal to a period represented by SOURCE(j) shown in Figure 3. In cases where usual line sequential scanning is performed, it is preferable that one output period is made equal to one horizontal period. The reason for this is as follows. While the data driver 102 outputs voltages corresponding to digital video data for one horizontal (scanning) line, to the data lines 106, it also performs sampling of digital video data for the next horizontal line. The maximum allowable length of time during which these voltages can be output from the data driver 102 is equal to one horizontal period. Furthermore, except for special cases, as the output period becomes longer, the pixels can be charged more accurately. In the driving circuit described herein, therefore, one output period is equal to one horizontal period. According to the present invention, however, one output period is not necessarily required to be equal to one horizontal period.

Figure 4 shows, in addition to the timings of the respective signals shown in Figures 2 and 3, the levels of voltages which are applied to the pixels P(j, i) (j = 1, 2, ..., M) in accordance with the timings.

Figure 5 shows an exemplary waveform for a voltage signal output from the data driver 102 to the data lines 106 in one output period. In the case of the conventional data driver, the voltage level of the voltage signal output to the data lines 106 is constant during one output period. On the other hand, from the data driver 102 in this example according to the invention, the voltage signal output to the data lines 106 includes an oscillating component which oscillates during one output period. As is shown in Figure 5, the voltage signal is a pulse-like signal, and a ratio of a high-level period to a low-level period, i.e., a duty ratio n:m is selected as described below.

Figure 6 shows a configuration of a part of the data driver 102 in the driving circuit 101. The circuit 60 shown in Figure 6 outputs a video signal from an nth output terminal S(n) to one data line 106. The data driver 102 includes circuits 60 the number of which is equal to the number of the data lines 106 provided in the display section 100. Herein, it is assumed that the video data consists of 6 bits (D₀, D₁, D₂, D₃, D₄, D₅). On such an assumption, the video data may have 64 kinds of values of 0 - 63, and a signal voltage applied to each pixel is one of nine gray-scale voltages V₀, V₈, V₁₆, V₂₄, V₃₂, V₄₀, V₄₈, V₅₆, and V₆₄, and interpolated voltages which are produced from any pair of the gray-scale voltages chosen from V₀, V₈, V₁₆, V₂₄, V₃₂, V₄₀, V₄₈, V₅₆, and V₆₄

The circuit 60 includes a sampling flip-flop M_SMP which performs the sampling operation, a holding flip-flop M_H which performs the holding operation, a selection control circuit SCOL, and analog switches ASW₀-ASW₈. To each of the analog switches ASW₀-ASW₈, a corresponding one of nine gray-scale voltages V₀, V₈, V₁₆, V₂₄, V₃₂, V₄₀, V₄₈, V₅₆, and V₆₄ is supplied. The gray-scale voltages V₀-V₆₄ have respective levels which are different from each other. The selection control circuit SCOL is provided with seven oscillating signals t₁-t₇. The oscillating signals t₁-t₇ have respective duty ratios which are different from each other.

As the sampling flip-flop M_SMP and the holding flip-flop M_H, for example, D-type flip-flops can be used. It is appreciated that such sampling and holding flip-flops can be realized by using other types of circuit elements.

Next, by referring to Figure 6, the operation of the circuit 60 is described. At the rising of a sampling pulse T_SMPn corresponding to the nth pixel, the sampling flip-flop M_SMP gets video data (D₀, D₁, D₂, D₃, D₄, D₅), and holds the video data therein. When such video data sampling for one horizontal period is completed, an output pulse signal OE is applied to the holding flip-flop M_H. When the output pulse signal OE is applied, the video data held in the sampling flip-flop M_SMP is fed into the holding flip-flop M_H and output to the selection control circuit SCOL. The selection control circuit SCOL receives the video data, and produces a plurality of control signals in accordance with the value of the video data. The control signals are used for switching the ON/OFF states of the respective analog switches ASW₀-ASW₈. The video data input to the selection control circuit SCOL is represented by d₀, d₁, d₂, d₃, d₄, and d₅, and the control signals output from the selection control circuit SCOL are represented by S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄.

Table 2 is a logical table for the lower three bits d₂, d₁, and d₀ of the 6-bit video data. The 1st to 3rd columns of Table 2 indicate the values of video data bits d₂, d₁, and d₀, respectively. The 4th to 11th columns of Table 2 indicate which oscillating signal is specified from the oscillating signals t₀-t₇. In the 4th to 11th columns of Table 2, the oscillating signal which is indicated by a value of 1 is specified. For example, in the case of (d₂, d₁, d₀) = (0, 0, 0), the oscillating signal t₀ is specified. In this example, the oscillating signals t₀-t₇ are clock signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7, respectively. Herein, if an oscillating signal has a duty ratio of k:0 or 0:k (k is a natural number), the oscillating signal is defined as always being at a fixed level. The oscillating signals t₅, t₆, and t₇ are the signals obtained by inverting the oscillating signals t₃, t₂, and t₁. d₂ d₁ d₀ t₀ t₁ t₂ t₃ t₄ t₅ t₆ t₇ 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1

From the logical table of Table 2, the following logical equation is obtained.$${\text{T = (0)t}}_{\text{0}}{\text{+ (1)t}}_{\text{1}}{\text{+ (2)t}}_{\text{2}}{\text{+ (3)t}}_{\text{3}}{\text{+ (4)t}}_{\text{4}}{\text{+ (5)t}}_{\text{5}}{\text{+ (6)t}}_{\text{6}}{\text{+ (7)t}}_{\text{7}}$$

In the above equation, (i) indicates a value of binary data (d₂, d₁, d₀) which is represented in a decimal notation. That is, (0) = (d₂, d₁, d₀) = (0, 0, 0), (1) = (d₂, d₁, d₀) = (0, 0, 1), (2) = (d₂, d₁, d₀) = (0, 1, 0), (3) = (d₂, d₁, d₀) = (0, 1, 1), (4) = (d₂, d₁, d₀) = (1, 0, 0), (5) = (d₂, d₁, d₀) = (1, 0, 1), (6) = (d₂, d₁, d₀) = (1, 1, 0), and (7) = (d₂, d₁, d₀) = (1, 1, 1).

The oscillating signal t₀ is continually at a level of "1", so that Equation (6) can alternatively be represented as the following equation.$${\text{T = (0) + (1)t}}_{\text{1}}{\text{+ (2)t}}_{\text{2}}{\text{+ (3)t}}_{\text{3}}{\text{+ (4)t}}_{\text{4}}{\text{+ (5)t}}_{\text{5}}{\text{+ (6)t}}_{\text{6}}{\text{+ (7)t}}_{\text{7}}$$

Table 3 is a logical table representing the relationships among the upper three bits d₅, d₄, and d₃ of the 6-bit video data, and the control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄. In Table 3, a variable T denotes a signal T which is defined by Equations (6) and (7). A variable $\overline{\text{T}}$ denotes an inverted signal $\overline{\text{T}}$ obtained by inverting the signal T. d₅ d₄ d₃ S₀ S₈ S₁₆ S₂₄ S₃₂ S₄₀ S₄₈ S₅₆ S₆₄ 0 0 0 T $\overline{\text{T}}$ 0 0 1 T $\overline{\text{T}}$ 0 1 0 T $\overline{\text{T}}$ 0 1 1 T $\overline{\text{T}}$ 1 0 0 T $\overline{\text{T}}$ 1 0 1 T $\overline{\text{T}}$ 1 1 0 T $\overline{\text{T}}$ 1 1 1 T $\overline{\text{T}}$

From the logical table of Table 3, the following logical equations are obtained.$${\text{S}}_{\text{0}}\text{= [0]T}$$$${\text{S}}_{\text{8}}\text{= [0]"T" + [8]T}$$$${\text{S}}_{\text{16}}\text{= [8]"T" + [16]T}$$$${\text{S}}_{\text{24}}\text{= [16]"T" + [24]T}$$$${\text{S}}_{\text{32}}\text{= [24]"T" + [32]T}$$$${\text{S}}_{\text{40}}\text{= [32]"T" + [40]T}$$$${\text{S}}_{\text{48}}\text{= [40]"T" + [48]T}$$$${\text{S}}_{\text{56}}\text{= [48]"T" + [56]T}$$$${\text{S}}_{\text{64}}\text{= [56]"T"}$$

In the above equations, [i] indicates a value of binary data (d₅, d₄, d₃), where i = (8 × j), and j is a value of binary data (d₅, d₄, d₃) which is represented in a decimal notation. For example, [8] = (d₅, d₄, d₃) = (0, 0, 1). In addition, "T" denotes an inverted signal of the signal T.

In accordance with the respective logical equations which are described above, logical circuits 70, 80, 90, and 95 shown in Figures 7 through 10 are obtained. The selection control circuit SCOL is constructed, for example, by the logical circuits 70, 80, 90, and 95 shown in Figures 7 through 10.

The logical circuit 70 shown in Figure 7 selectively outputs oscillating signal specifying signals (0)-(7) for specifying one of a plurality of oscillating signals t₀-t₇, in accordance with the lower 3 bits d₂, d₁, and d₀ of the video data. More specifically, the video data d₂, d₁, and d₀ and the inverted signals which are respectively obtained by inverting the video data d₂, d₁, and d₀ by inverter circuits INV₀ to INV₂ are input into AND circuits AG₀-AG₇ in such combinations that constitute 0-7 in binary notation. The oscillating signal specifying signals (0)-(7) are thus obtained as the outputs of the AND circuits AG₀-AG₇.

The logical circuit 80 shown in Figure 8 specifies one of the plurality of oscillating signals t₀-t₇ in accordance with the oscillating signal specifying signals, and produces the specified oscillating signal T and the inverted oscillating signal $\overline{\text{T}}$ which is obtained by inverting the specified oscillating signal T by an inverter circuit INV₃. More specifically, the oscillating signal specifying signals (1)-(7) and the oscillating signals t₁-t₇ are input into AND circuits BG₁-BG₇, respectively, as is shown in Figure 8. The oscillating signal specifying signal (0) and the outputs of the AND circuits BG₁-BG₇ are supplied to an OR circuit CG. The oscillating signal T and the inverted oscillating signal $\overline{\text{T}}$ are obtained as the output of the OR circuit CG.

The logical circuit 90 shown in Figure 9 selectively outputs gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56] for specifying a pair of gray-scale voltages from among a plurality of gray-scale voltages, in accordance with the upper three bits d₅, d₄, and d₃ of the video data. More specifically, the video data d₅, d₄, and d₃ and the inverted signals which are respectively obtained by inverting the video data d₅, d₄, and d₃ by inverter circuits INV₄-INV₆ are input to AND circuits DG₀-DG₇ in such combinations which constitute 0-7 in the binary notation. As the outputs of the AND circuits DG₀-DG₇, the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56] are obtained.

The logical circuit 95 shown in Figure 10 selectively outputs the control signals S₀-S₆₄, in accordance with the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56], the oscillating signal T, and the inverted oscillating signal $\overline{\text{T}}$. More specifically, the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56], and the oscillating signal T are input into AND circuits EG₀, EG₂, EG₄, EG₆, EG₈, EG₁₀, EG₁₂, and EG₁₄, respectively. The gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56] and the inverted oscillating signal $\overline{\text{T}}$ are input into AND circuits EG₁, EG₃, EG₅, EG₇, EG₉, EG₁₁, EG₁₃, and EG₁₅, respectively. The outputs of the AND circuits EG₁ and EG₂ are coupled to the inputs of an OR circuit FG₁, respectively. The outputs of the AND circuits EG₃ and EG₄ are coupled to the inputs of an OR circuit FG₂, respectively. The outputs of the AND circuits EG₅ and EG₆ are coupled to an OR circuit FG₃, respectively. The outputs of the AND circuits EG₇ and EG₈ are coupled to the inputs of an OR circuit FG₄, respectively. The outputs of the AND circuits EG₉ and EG₁₀ are coupled to the inputs of an OR circuit FG₅, respectively. The outputs of the AND circuits EG₁₁ and EG₁₂ are coupled to the inputs of an OR circuit FG₆, respectively. The outputs of the AND circuits EG₁₃ and EG₁₄ are coupled to the inputs of an OR circuit FG₇, respectively. As the outputs of the AND circuit EG₀, the OR circuits FG₁-FG₇, and the AND circuit EG₁₅, the control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄ are obtained.

The control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄ are supplied to the corresponding analog switches ASW₀-ASW₈. Each of the control signals S₀, S₈, S₁₆, S₂₄, S₃₂, S₄₀, S₄₈, S₅₆, and S₆₄ has either a high-level value or a low-level value. For example, if the control signal is at a high level, the corresponding analog switch is controlled to be in the ON-state. If the control signal is at a low level, the corresponding analog switch is controlled to be in the OFF-state. Alternatively, the relationship between the level of the control signal and the ON/OFF state of the analog signal can be set in a reverse manner.

As described above, in the case where video data consists of a plurality of bits, a waveform of an oscillating voltage is specified in accordance with video data consisting of at least one bit selected from the plurality of bits. Then, in accordance with video data consisting of bits other than the above selected bit(s), a pair of gray-scale voltages are specified from a plurality of gray-scale voltages. As a result, a voltage signal of an appropriate level can be output for every value of video data. The oscillating voltage is used for realizing a plurality of interpolated gray-scale voltages between the specified pair of gray-scale voltages which are specified from among the plurality of gray-scale voltages.

In the case where the value of the video data is a multiple of 8, only one of the plurality of gray-scale voltages may be output. In such a case, the duty ratio n:m of the oscillating signal or the control signal is interpreted to be k:0 or 0:k (k is a natural number).

Alternatively, regardless of whether the value of the video data is a multiple of 8 or not, the specified pair of gray-scale voltages among the plurality of gray-scale voltages may be alternately output.

As described above, the selection control circuit SCOL according to the invention constructed of the logical circuits 70, 80, 90, and 95 shown in Figures 7 through 10 has a simplified construction as compared with the conventional selection control circuit SCOL shown in Figure 12 which is constructed of the logical circuits shown in Figures 14 and 15. According to the invention, it is possible to display an image with multiple gray scales, such as 64 gray scales, by using a driving circuit having a more simplified construction. For example, in order to realize a display image with 64 gray scales, only 9 kinds of gray-scale voltages are required.

The actual data driver requires selection control circuits SCOL the number of which is equal to the number of data lines. Thus, the circuit scale of the selection control circuits SCOL largely affects the chip size of an integrated circuit (LSI) on which a data driver is installed. According to the invention, it is possible to significantly reduce the size of the integrated circuit including the selection control circuits SCOL. As a result, the production cost of the integrated circuit can be reduced. In cases where the number of bits of video data is increased in order to realize an image with a larger number of gray scales, such miniaturization of the circuit scale of the data driver is of great use. Accordingly, it is possible to make further progress in the size and cost reduction of the integrated circuit.

According to the invention, it is possible to obtain one or more interpolated voltages from voltages supplied from given voltage sources, whereby the number of voltage sources can be greatly decreased as compared with a conventional driving circuit which requires a large number of voltage sources. If the voltage sources are provided from the outside of the driving circuit, the number of input terminals of the driving circuit can be reduced. If the driving circuit is constructed as an LSI, the number of input terminals of the LSI can be reduced. According to the invention, it is possible to realize a driving LSI for displaying an image with multiple gray scales which could not be realized by the prior art example because of the increase in the number of terminals. In the present invention, the following effects can be attained: (1) the production cost of a display apparatus and a driving circuit are largely reduced; (2) a driving circuit for multiple gray scales which could not be practically produced due to the chip size or the LSI installation can be readily produced; and (3) the power consumption is decreased because a large number of voltage sources are not required.

Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope of this invention. Accordingly, it is not intended that the scope of the invention be limited to the description as set forth herein, but rather by the appended claims.