Passively-multiplexed resistor array

Description

[0001] The present invention relates to the field of passively-multiplexed resistor arrays. More specifically, the present invention pertains to decreasing the peak power dissipated by unselected resistors in a passively-multiplexed resistor array.

Related Art

[0002] Large resistors arrays are used in many applications. Two examples are thermal printheads used to print on thermal paper or used in thermal transfer printing and thermal ink-jet printheads. In these applications, electric currents are driven through selected resistors in the resistor array to "mark" the print medium at a specific location.

[0003] Because these resistor arrays can comprise large numbers of resistors, directly driving each resistor is typically impractical. Thus, some form of multiplexing may be used, thereby decreasing the number of leads required to control the resistors.

[0004] One type of multiplexing is known as "passive multiplexing," and is shown in FIG. 1. In the exemplary passively-multiplexed resistor array shown, a plurality of resistors R₁₁-R₆₄ are connected in an array having six rows 12a-12f and four columns 10a-10d.

[0005] The columns 10a-10d may be selectively connected to a voltage source 16 via column switches 18a-18d. Each column 10a-10d can be "activated" in turn by closing its respective column switch. In passive multiplexing, only one column switch may be closed at one time; the other column switches must be open. The rows 12a-12f may be selectively connected to ground via switches 20a-20f. Each row 12a-12f can be selected by closing its respective switch. Multiple rows may be selected simultaneously.

[0006] Each resistor R₁₁-R₆₄ bridges a respective intersection of the rows 12a-12f and columns 10a-10d. By activating a column and selecting a row, the resistor which bridges the activated column and selected row thereby has a voltage imposed across it and is thus directly driven. In FIG. 1, the first column 10a is shown activated and the first and third rows 12a and 12c are shown selected. Thus, resistors R11 and R31 are shown directly driven.

[0007] In the schematic diagram of FIG. 1, the resistors R₁₁-R₆₄ are shown in a rectangular arrangement. This graphical arrangement is selected only for the convenience of this description. The resistors may be physically arrayed in any arbitrary arrangement provided that the electrical connections remain as shown. For example, the resistors could be arranged in a line for a thermal printhead or a pair of lines for a thermal ink-jet printhead.

[0008] In a passively-multiplexed resistor array, current can flow through every resistor R₁₁-R₆₄ in the array. For example, referring to FIG. 1, with the switches in the states shown, "parasitic" current flows along the first column 10a, through resistor R₂₁, along the second row 12b, through resistor R₂₂, along the second column 10b, through resistor R₁₂, and along the first row to the ground via the first row switch 20a.

[0009] One problem with the parasitic current is that an unselected resistor may receive enough parasitic energy to "fire." That is, the resistor may generate enough heat to mark the media in thermal printheads or to eject ink in ink-jet printheads. What is needed is a passively-multiplexed resistor array which decreases the amount of energy dissipated by an unselected resistor.

[0010] GB-A-2031805 describes a thermal printing device incorporating an array of resistors which are selectively energized to effect printing of dots on a heat-sensitive paper. The problem of temperatures generated by "sneak" currents being sufficient to mark the paper is acknowledged, but this problem is stated to be overcome without the need for additional diodes or other electronic elements to be provided.

[0011] It would be desirable to provide a passively-multiplexed resistor array which decreases the parasitic power dissipated through unselected resistors.

[0012] In accordance with a first aspect of the present invention, there is provided a passively-multiplexed resistor array as defined by Claim 1.

[0013] In accordance with a second aspect of the present invention, there is provided a method for decreasing the peak parasitic power dissipated by unselected resistors in a passively-multiplexed resistor array, as defined by Claim 6.

[0014] The present invention is thus directed to a passively-multiplexed resistor array having at least one row of "minimizer" resistors. These minimizer resistors may be selected to decrease the parasitic power dissipated through unselected resistors.

[0015] These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description and appended claims.

Brief Description of the Drawings

[0016] FIG. 1 shows a schematic diagram of a prior art passively-multiplexed resistor array.

[0017] FIG. 2 shows the resistor array of FIG. 1 rearranged to show more clearly the parasitic currents.

[0018] FIG. 3 shows a passively-multiplexed resistor array according to the present invention having a single row of minimizer resistors.

[0019] FIG. 4 shows the passively-multiplexed resistor array of FIG. 3, further comprising a second row of minimizer resistors.

[0020] FIG. 5 shows the "transposed" case of FIG. 3, having a single column of minimizer resistors.

Detailed Description of the Invention

[0021] FIG. 2 shows the circuit of FIG. 1 rearranged to show the parasitic current paths. The first column switch 18a is closed, thereby activating the first column 10a. The other column switches 18b-18d are open. The first and third row switches 20a and 20c are closed, thereby selecting the first and third rows 12a and 12c and directly driving resistors R₁₁ and R₃₁. The directly driven, or "fired" resistors are generally designated by reference Rf. The other row switches 20b and 20d-20f are open.

[0022] In addition to the directly-driven resistors R₁₁ and R₃₁, current also flows through the other, unselected resistors R₂₁ and R₄₁-R₆₁ connected to the first column 10a. These resistors are designated generally in FIG. 2 by reference R_c. From there, the current flows through the resistors which are neither in an activated column nor in a selected row, generally designated by reference R_u. Finally, the current flows through the resistors in the selected rows, generally designated by reference R_r, back to ground.

[0023] In many applications, all of the resistors in the array have the same resistance. For thermal ink-jet printing, designing the printhead such that the resistances (as well as other parameters) are equal ensures that the printhead provides uniform performance for the numerous nozzles. Thus, for the rest of this discussion, the resistors in the resistor array will be assumed to be of equal resistance. In such a case, it is much simpler to obtain solutions for the parasitic currents through the resistors which are not directly driven.

[0024] To represent these solutions mathematically, the following symbols are defined:

Rows

= the number of rows in the array

Columns

= the number of columns in the array

N

= the number of activated resistors in the selected column

R

= the value of any resistor in the array

[0025] Because of symmetry, the second through fourth columns 10b-10d can be considered as though they were interconnected. Thus the total resistance R_c,t of the resistors R_c in the active column which are not selected is simply the parallel combination of the resistances and is given in the following equation:

[0026] Similarly, the total resistance R_u,t of the unrelated resistors R_u not in the active column nor in a selected row is given in the following equation:

[0027] And finally, the total resistance R_r,t of the resistors R_r not in the active column but in a selected row is given in the following equation:

[0028] The power through the directly-driven resistors R₁₁ and R₃₁ is:

[0029] The total power through the resistors R_c in the active column which are not selected is given by:

[0030] Thus, the power through a single, unselected resistor R_c in the active column is:

[0031] Dividing by V²/R normalizes the resulting value to the power dissipated by a directly-driven resistor R_f, and results in the ratio:

[0032] Likewise, the equations for the powers through the resistors R_u in rows and columns unrelated to selected resistors, and for resistors R_r in the selected rows, respectively, are:

[0033] Using the equations given above, the relative powers dissipated through the parasitic currents can be calculated. Results of the calculations for the unselected resistors R_c in the active column, the unrelated resistors R_u which are not in the active column nor in a selected row, and the resistors R_r in the selected rows, for various numbers N of directly-driven resistors, are shown in Table 1.

Table 1

N	1	2	3	4	5	6
Pc/Pf	11.1%	25.0%	36.0%	44.4%	51.0%	0.0%
Pu/Pf	1.2%	2.8%	4.0%	4.9%	5.7%	0.0%
Pr/Pf	30.9%	11.1%	4.0%	1.2%	0.2%	0.0%

[0034] As shown by Table 1, when five resistors are being directly driven (N = 5), then the unselected resistor R_c in the active column dissipates 51.0 percent of the energy dissipated by one directly-driven resistor. This value is large enough to likely cause a thermal printhead to print or a thermal ink-jet printhead to eject ink.

[0035] Equations 7-9 show that the maximum parasitic power dissipated through an unselected resistor is dependent on the size of the resistor array and the number of resistors being directly driven. This fact can be used to minimize the maximum parasitic power dissipated through an unselected resistor.

[0036] Referring now to FIG. 3, a passively-multiplexed resistor array according to the present invention is shown. As in the prior art, the resistor array has resistors R₁₁-R₆₄ electrically arranged into six rows 12a-12f and four columns 10a-10d. Likewise, row switches 20a-20f and column switches 18a-18d selectively connect the rows and columns to ground and a voltage source 16, respectively.

[0037] The resistor array further includes an extra row 12g of "minimizer" resistors R₇₁-R₇₄. These minimizer resistors, although electrically connected in the resistor array, do not perform the function of the other resistors in the array. In the preferred embodiment, the resistor array is included in a thermal printhead or thermal ink-jet printhead. The resistors R₁₁-R₆₄ enclosed by the dashed line 14 generate heat which is used to print. The minimizer resistors R₇₁-R₇₄, although they do generate heat, are physically arranged such that they do not cause printing, or if in a thermal ink-jet printhead, the minimizer resistors do not cause ink to eject from a nozzle. Rather, these minimizer resistors may be selectively fired to decrease the maximum energy dissipated in other, unselected resistors which otherwise perform a printing function.

[0038] There is no requirement that the minimizer resistors R₇₁-R₇₄ even be located on the printhead. As long as the electrical connections remain as shown in FIG. 3, the physical arrangement may be changed.

[0039] Using equations 7-9, the relative dissipated powers for resistors R_c, R_u, and R_r are calculated for different numbers N of rows simultaneously selected and are listed in Table 2. Although only six rows of resistors are used for printing, the seventh, minimizer row is included in the table since it may be selectively fired.

Table 2

N	1	2	3	4	5	6	7
Pc/Pf	9.0%	21.3%	31.6%	39.9%	46.5%	51.8%	0.0%
Pu/Pf	1.0%	2.4%	3.5%	4.4%	5.2%	5.8%	0.0%
Pr/Pf	36.0%	14.8%	6.3%	2.5%	0.8%	0.2%	0.0%

[0040] To decrease the parasitic currents, the minimizer row 12g is selected any time one or six other resistors are driven in the active column. For example, if row switch 20b is closed, selecting the second row, and the other row switches 20a and 20c-20f are open, then minimizer row switch 20g will be closed to have two resistors will be selected (N = 2). Likewise, if all six row switches 20a-20f are closed, then minimizer row switch 20g will be closed to have all resistors selected (N = 7). One or six total resistors will never be selected simultaneously. Therefore, the worst-case parasitic power to an unselected resistor is 46.5 percent of a directly-driven resistor which occurs when N equals five.

[0041] Referring now to FIG. 4, another passively-multiplexed resistor array according to the present invention is shown. As in the prior art, the resistor array has resistors R₁₁-R₆₄ electrically arranged into six rows 12a-12f and four columns 10a-10d. Likewise, row switches 20a-20f and column switches 18a-18d selectively connect the rows and columns to ground and a voltage source 16, respectively.

[0042] The resistor array further includes two extra rows 12g-12h of minimizer resistors R₇₁-R₈₄. As in the case of a single row of minimizer resistors, these minimizer resistors do not perform a printing function.

[0043] Table 3 shows the power dissipated in unselected resistors as a percentage of the power dissipated in directly-driven resistors for different numbers N of simultaneously selected rows.

Table 3

N	1	2	3	4	5	6	7	8
Pc/Pf	7.4%	18.4%	28.0%	36.0%	42.5%	47.9%	52.4%	0.0%
Pu/Pf	0.8%	2.0%	3.1%	4.0%	4.7%	5.3%	5.8%	0.0%
Pr/Pf	40.5%	18.4%	8.7%	4.0%	1.7%	0.6%	0.1%	0.0%

[0044] The minimizer resistors are selected such that one, two, six, or seven resistors are never fired simultaneously in one column. For example, if one row switch 20f is closed to select row 20f, and row switches 20-20a are open, then minimizer row switches 20g and 20h will be closed such that N equals three. In this manner, the worst case parasitic power to an unselected resistor is 42.5 percent.

[0045] The present invention has been described in conjunction with thermal printheads and thermal ink-jet printheads. It will be understood by one of ordinary skill in the field that the invention is applicable to any passively-multiplexed resistor array.

[0046] There is no requirement that the minimizer resistors be located on a printhead or off the printhead. Rather, the requirement is that the minimizer resistors be electrically connected as an additional row which may be selected.

[0047] The present invention has been described with activated columns where a plurality of rows may be simultaneously selected. The invention is applicable in cases where only one "functional" resistor can be driven at once, with the minimizer resistor being driven to decrease the power dissipated through the unselected resistors.

[0048] The invention is equally applicable in the "transposed" case where a single row is activated and a column or columns may be selected.

[0049] In such a case, an additional column or additional columns of minimizer resistors may be used in a manner parallel to that described above. Fig. 5 shows such an arrangement. An additional column 10e, with its associated switch 18e, is added to the structure of Fig. 1. Across the intersections of this column with the rows, a column of minimizer resistors R₁₅-R₆₅ is connected in a similiar manner and for the purposes already described. In Fig. 5, switch 20a is closed, selecting row 12a. Likewise, switches 18a and 18c are closed, activating columns 10a and 10c. The operation of the circuit may be understood by considering this arrangement as the transpose of Fig. 3, and applying the detailed explanation of that circuit.

[0050] Similiarly, the voltage source 16 may be interchanged with the ground connection in all the illustrated circuits with no effect on the principles of operation.

[0051] The resistor arrays shown in FIGS. 3, 4, and 5 are completely filled; that is, there is a resistor at each intersection of a row and column conductor. The present invention is applicable to resistor arrays which are sparsely populated, with no resistors at some intersections.

[0052] Therefore, the scope of the appended claims should not be limited to the description of the preferred versions contained herein.

Claims

1. A passively-multiplexed resistor array, comprising:

(a) a power source (16);

(b) a plurality of m row (12a-12f) or column (10a-10d) conductors;

(c) a plurality of n column (10a-10d) or row (12a-12f) conductors, wherein the row conductors (12a-12f) and column conductors (10a-10d) are electrically arranged to form a grid having m x n intersections;

(d) a plurality of array resistors (R₁₁-R₆₄), each of which is connected between a respective intersection of the m row (12a-12f) or column (10a-10d) conductors and the n column (10a-10d) or row (12a-12f) conductors for selectively receiving power from said power source (16); and

(e) an (m+1)th row (12g; 12g,12h) or column (10e) conductor arranged to intersect the n column (10a-10d) or row (12a-12f) conductors; characterised in that said array further comprises:

(f) a plurality of n minimiser resistors (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅), each of which is connected between a respective intersection of the (m+1)th row (12g; 12g,12h) or column (10e) conductor and the n column (10a-10d) or row (12a-12f) conductors; and

(g) means for controlling the power source (16) to energize selectively the (m+1)th row (12g; 12g,12h) or column (10e) conductor with one or more of said m row (12a-12f) or column (10a-10d) conductors, thereby to minimize the peak parasitic power absorbed by an unselected array resistor.

2. A passively-multiplexed resistor array as claimed in Claim 1, wherein said plurality of array resistors includes m x n resistors (R₁₁-R₆₄).

3. A passively-multiplexed resistor array as claimed in Claim 1 or Claim 2, further comprising:

(a) an (m+2)th row (12g) or column conductor arranged to intersect the n column (10a-10d) or row (12a-12f) conductors;

(b) a second plurality of n minimizer resistors (R₈₁-R₈₄), each of which is connected between a respective intersection of the (m+2)th row (12g) or column conductor and the n column (10a-10d) or row (12a-12f) conductors.

4. A passively-multiplexed resistor array as claimed in any preceding claim wherein said plurality of array resistors (R₁₁-R₆₄) have substantially the same resistance.

5. A passively-multiplexed resistor array as claimed in any preceding claim, wherein said plurality of array resistors (R₇₁-R₆₄) and said minimiser resistors (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅) have substantially the same resistance.

6. A method for decreasing the peak parasitic power dissipated by unselected resistors in a passively-multiplexed resistor array having m rows (12a-12f) or columns (10a-10d) and n columns (10a-10d) or rows (12a-12f) of conductors, array resistors (R₁₁-R₆₄) connected between column and row intersections and an electrical source (16) for supplying power to selected resistors (e.g. R₁₁) by energizing corresponding rows and columns, characterised in that the method comprises the steps of:

(a) providing an (m+1)th row (12g; 12g,12h) or column (10e) conductor with minimizer resistors (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅) connected between said (m+1)th row (12g; 12g,12h) or column (10e) and said n columns (10a-10d) or rows (12a-12f) of conductors;

(b) selectively energizing said (m+1)th row (12g; 12g,12h) or column (10e) conductor with one or more of said m row (12a-12f) or column (10a-10d) conductors, thereby to decrease the peak parasitic power dissipated by unselected array resistors.

7. A method as claimed in Claim 6, wherein the array resistors (R₁₁-R₆₄) have substantially the same resistance.

8. A method as claimed in Claim 6 or Claim 7, wherein the array resistors (R₁₁-R₆₄) and the minimizer resistors (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅) have substantially the same resistance.

Ansprüche

1. Ein passiv multiplexiertes Widerstandsarray mit folgenden Merkmalen:

(a) einer Leistungsquelle (16);

(b) einer Mehrzahl von m Zeilen- (12a-12f) oder Spalten- (10a-10d) Leitern;

(c) einer Mehrzahl von n Spalten- (10a-10d) oder Zeilen- (12a-12f) Leitern, wobei die Zeilenleiter (12a-12f) und die Spaltenleiter (10a-10d) elektrisch angeordnet sind, um ein Gitter mit m x n Schnittpunkten zu bilden;

(d) einer Mehrzahl von Arraywiderständen (R₁₁-R₆₄), wobei jeder derselben zwischen einen jeweiligen Schnittpunkt der m Zeilen- (12a-12f) oder Spalten-(10a-10d) Leiter und der n Spalten- (10a-10d) oder Zeilen- (12a-12f) Leiter geschaltet ist, zum selektiven Empfangen von Leistung von der Leistungsquelle (16); und

(e) einem (m+1)ten Zeilen- (12g; 12g, 12h) oder Spalten- (10e) Leiter, der angeordnet ist, um die n Spalten- (10a-10d) oder Zeilen- (12a-12f) Leiter zu schneiden; dadurch gekennzeichnet, daß das Array ferner folgende Merkmale aufweist:

(f) eine Mehrzahl von n Minimiererwiderständen (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅), wobei jeder derselben zwischen einen jeweiligen Schnittpunkt des (m+1)ten Zeilen- (12g; 12g, 12h) oder Spalten-(10e) Leiters und der n Spalten- (10a-10d) oder Zeilen- (12a-12f) Leiter geschaltet ist; und

(g) eine Einrichtung zum Steuern der Leistungsquelle (16), um selektiv den (m+1)ten Zeilen- (12g; 12g, 12h) oder Spalten- (10e) Leiter mit einem oder mehreren der m Zeilen- (12a-12f) oder Spalten-(10a-10d) Leiter zu erregen, um dadurch die parasitäre Spitzenleistung zu minimieren, die durch einen nicht ausgewählten Arraywiderstand absorbiert wird.

2. Ein passiv multiplexiertes Widerstandsarray gemäß Anspruch 1, bei dem die Mehrzahl von Arraywiderständen m x n Widerstände (R₁₁-R₆₄) aufweist.

3. Ein passiv multiplexiertes Widerstandsarray gemäß Anspruch 1 oder 2, mit ferner folgenden Merkmalen:

(a) einem (m+2)ten Zeilen- (12g) oder Spalten-Leiter, der angeordnet ist, um die n Spalten- (10a-10d) oder Zeilen- (12a-12f) Leiter zu schneiden;

(b) einer zweiten Mehrzahl von n Minimiererwiderständen (R₈₁-R₈₄), wobei jeder derselben zwischen einen jeweiligen Schnittpunkt des (m+2)ten Zeilen-(12g) oder Spalten-Leiters und der n Spalten-(10a-10d) oder Zeilen- (12a-12f) Leiter geschaltet ist.

4. Ein passiv multiplexiertes Widerstandsarray gemäß einem beliebigen der vorhergehenden Ansprüche, bei dem die Mehrzahl von Arraywiderständen (R₁₁-R₆₄) im wesentlichen den gleichen Widerstand aufweist.

5. Ein passiv multiplexiertes Widerstandsarray gemäß einem beliebigen der vorhergehenden Ansprüche, bei dem die Mehrzahl von Arraywiderständen (R₁₁-R₆₄) und die Minimiererwiderstände (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅) im wesentlichen den gleichen Widerstand aufweisen.

6. Ein Verfahren zum Verringern der parasitären Spitzenleistung, die durch nicht ausgewählte Widerstände in einem passiv multiplexierten Widerstandsarray mit m Zeilen (12a-12f) oder Spalten (10a-10d) und n Spalten (10a-10d) oder Zeilen (12a-12f) von Leitern dissipiert wird, wobei die Arraywiderstände (R₁₁-R₆₄) zwischen Spalten- und Zeilen-Schnittpunkte und eine elektrische Quelle (16) geschaltet sind, zum Liefern von Leistung zu ausgewählten Widerständen (z. B. R₁₁) durch Erregen von entsprechenden Zeilen und Spalten, dadurch gekennzeichnet, daß das Verfahren folgende Schritte aufweist:

(a) Bereitstellen eines (m+1)ten Zeilen- (12g; 12g, 12h) oder Spalten- (10e) Leiters mit Minimiererwiderständen (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅), die zwischen die (m+1)te Zeile (12; 12g, 12h) oder Spalte (10e) und die n Spalten (10a-10d) oder Zeilen (12a-12f) von Leitern geschaltet sind;

(b) selektives Erregen des (m+1)ten Zeilen- (12g; 12g, 12h) oder Spalten- (10e) Leiters mit einem oder mehreren der m Zeilen- (12a-12f) oder Spalten-(10a-10d) Leiter, um dadurch die parasitäre Spitzenleistung zu verringern, die durch nicht ausgewählte Arraywiderstände dissipiert wird.

7. Ein Verfahren gemäß Anspruch 6, bei dem die Arraywiderstände (R₁₁-R₆₄) den im wesentlichen gleichen Widerstandswert aufweisen.

8. Ein Verfahren gemäß Anspruch 6 oder 7, bei dem die Arraywiderstände (R₁₁-R₆₄) und die Minimiererwiderstände (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅) den im wesentlichen gleichen Widerstand aufweisen.

Revendications

1. Réseau de résistances multiplexé de façon passive, comprenant :

(a) une source d'alimentation (16) ;

(b) une pluralité de m conducteurs en rangées (12a-12f) ou colonnes (10a-10f) ;

(c) une pluralité de n conducteurs en colonnes (10a-10d) ou rangées (12a-12f), dans lequel les conducteurs en rangées (12a-12f) et les conducteurs en colonnes (10a-10d) sont agencés électriquement de manière à former une grille ayant m x n intersections ;

(d) une pluralité de résistances de réseau (R₁₁-R₆₄), chacune d'entre elles étant connectée entre une intersection respective des m conducteurs en rangées (12a-12f) ou colonnes (10a-10d) et des n conducteurs en colonnes (10a-10d) ou rangées (12a-12f), pour recevoir de façon sélective de l'énergie de ladite source d'alimentation (16) ; et

(e) un conducteur de (m+1)-ième rangée (12g; 12g, 12h) ou colonne (10e) agencé pour couper les n conducteurs en colonnes (10a-10d) ou rangées (12a-12f) ; caractérisé en ce que ledit réseau comprend en outre :

(f) une pluralité de n résistances de minimisation (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅), chacune d'entre elles étant connectée entre une intersection respective du conducteur de la (m+1)-ième rangée (12g; 12g, 12h) ou colonne (10e) et des n conducteurs en colonnes (10a-10d) ou rangées (12a-12f) ; et

(g) des moyens pour commander la source d'alimentation (16) pour exciter de manière sélective le conducteur de la (m+1)-ième rangée (12g; 12g, 12h) ou colonne (10e) avec un ou plusieurs desdits m conducteurs en rangées (12a-12f) ou colonnes (10a-10f), de façon à minimiser la puissance parasite de crête absorbée par une résistance du réseau non-sélectionnée.

2. Réseau de résistances multiplexé de façon passive selon la revendication 1, dans lequel ladite pluralité de résistances de réseau comporte m x n résistances (R₁₁-R₆₄).

3. Réseau de résistances multiplexé de façon passive selon la revendication 1 ou la revendication 2, comprenant en outre :

(a) un conducteur de (m+2)-ième rangée (12g) ou colonne, agencé pour couper les n conducteurs en colonnes (10a-10d) ou rangées (12a-12f) ;

(b) une deuxième pluralité de n résistances de minimisation (R₈₁-R₈₄), chacune d'entre elles étant connectée entre une intersection respective du conducteur de la (m+2)-ième rangée (12g) ou colonne et des n conducteurs en colonnes (10a-10d) ou rangées (12a-12f).

4. Réseau de résistances multiplexé de façon passive selon l'une quelconque des revendications précédentes, dans lequel les résistances de ladite pluralité de résistances de réseau (R₁₁-R₆₄) ont sensiblement la même valeur de résistance.

5. Réseau de résistances multiplexé de façon passive selon l'une quelconque des revendications précédentes, dans lequel les résistances de ladite pluralité de résistances de réseau (R₁₁-R₆₄) et desdites résistances de minimisation (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅) ont sensiblement la même valeur de résistance.

6. Procédé pour diminuer la puissance parasite crête dissipée par des résistances non-sélectionnées situées dans un réseau de résistances multiplexé de façon passive comportant m rangées (12a-12f) ou colonnes (10a-10f) et n colonnes (10a-10d) ou rangées (12a-12f) de conducteurs, des résistances de réseau (R₁₁-R₆₄) connectées entre des intersections de colonnes et de rangées et une source électrique (16) pour délivrer de l'énergie aux résistances sélectionnées (par exemple, R₁₁) en excitant les rangées et colonnes correspondantes, caractérisé en ce que le procédé comprend les étapes consistant à :

(a) fournir à un conducteur de la (m+1)-ième rangée (12g; 12g, 12h) ou colonne (10e) des résistances de minimisation (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅), connectées entre ladite (m+1)-ième rangée (12g; 12g, 12h) ou colonne (10e) et lesdites n colonnes (10a-10d) ou rangées (12a-12f) de conducteurs ;

(b) exciter de manière sélective ledit conducteur de la (m+1)-ième rangée (12g; 12g, 12h) ou colonne (10e) avec un ou plusieurs desdits m conducteurs en rangées (12a-12f) ou colonnes (10a-10f), de façon à diminuer la puissance parasite crête dissipée par des résistances du réseau non-sélectionnées.

7. Procédé selon la revendication 6, dans lequel les résistances du réseau (R₁₁-R₆₄) ont sensiblement la même valeur de résistance.

8. Procédé selon la revendication 6 ou la revendication 7, dans lequel les résistances du réseau (R₁₁-R₆₄) et les résistances de minimisation (R₇₁-R₇₄; R₇₁-R₇₄, R₈₁-R₈₄; R₁₅-R₆₅) ont sensiblement la même valeur de résistance.

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