(19)
(11) EP 0 645 802 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
11.03.1998 Bulletin 1998/11

(43) Date of publication A2:
29.03.1995 Bulletin 1995/13

(21) Application number: 94306862.7

(22) Date of filing: 20.09.1994
(51) International Patent Classification (IPC)6: H01L 21/316, H01L 21/336
(84) Designated Contracting States:
DE FR GB NL

(30) Priority: 20.09.1993 JP 256563/93
20.09.1993 JP 256565/93
20.09.1993 JP 256567/93
19.10.1993 JP 284287/93

(71) Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Atsugi-shi Kanagawa-ken, 243 (JP)

(72) Inventors:
  • Konuma, Toshimitsu
    Atsugi-shi, Kanagawa-ken 243 (JP)
  • Sugawara, Akira
    Atsugi-shi, Kanagawa-ken 243 (JP)
  • Uehara, Yukiko
    Atsugi-shi, Kanagawa-ken 243 (JP)
  • Zhang, Hongyong
    Yamato-shi, Kanagawa-ken 242 (JP)
  • Suzuki, Atsunori
    Kawasaki-shi, Kanagawa-ken 214 (JP)
  • Ohnuma, Hideto
    Atsugi-shi, Kanagawa-ken 243 (JP)
  • Yamaguchi, Naoaki
    Yokohama-shi, Kanagawa-ken 222 (JP)
  • Suzawa, Hideomi
    Atsugi-shi, Kanagawa-ken 243 (JP)
  • Uochi, Hideki
    Atsugi-shi, Kanagawa-ken 243 (JP)
  • Takemura, Yasuhiko
    Atsugi-shi, Kanagawa-ken 243 (JP)

(74) Representative: Milhench, Howard Leslie et al
R.G.C. Jenkins & Co. 26 Caxton Street
London SW1H 0RJ
London SW1H 0RJ (GB)

   


(54) Semiconductor device and method for manufacturing the same


(57) A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an loff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode ; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.






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