(19)
(11) EP 0 663 768 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
16.08.1995 Bulletin 1995/33

(43) Date of publication A2:
19.07.1995 Bulletin 1995/29

(21) Application number: 95100547.9

(22) Date of filing: 17.01.1995
(51) International Patent Classification (IPC)6: H04N 5/44
(84) Designated Contracting States:
DE FR GB IT NL

(30) Priority: 18.01.1994 US 183534

(71) Applicant: TEXAS INSTRUMENTS INCORPORATED
Dallas Texas 75265 (US)

(72) Inventor:
  • Gove, Robert J. COMPRESSION LABS
    San Jose, CA 95134-1900 (US)

(74) Representative: Schwepfinger, Karl-Heinz, Dipl.-Ing. 
Prinz & Partner, Manzingerweg 7
D-81241 München
D-81241 München (DE)


(56) References cited: : 
   
       


    (54) Method and digital circuit for the line deinterlacing of displayed video images


    (57) A pixel generator and method of generating pixel data for creating frames of video pixel data from fields of input video pixel data. The pixel processor 16 includes a field buffer circuit 36 that stores a plurality of fields of input video pixel data. Coupled to the field buffer are a feature detector 38 and a pixel generator 40. The feature detector 38 generates one or more feature magnitude signals based upon one or more of the fields of input video pixel data. The pixel generator 40 has at least two logic circuits for generating at least two different intermediate pixel data values based on the input pixel data. Coupled to feature detector 38 is feature analyzer 42 that selects a feature weight corresponding to each intermediate pixel data value, the weight being based upon the value of the feature magnitude signals. Coupled to feature analyzer 42 and pixel generator 40, is a pixel averager 44 that generates output pixel data based upon a weighted average of the intermediate pixel data values.






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