Controller for a display with multiple common lines for each pixel

(19)

(11)

EP 0 673 012 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	10.01.1996 Bulletin 1996/02

(43)	Date of publication A2:
	20.09.1995 Bulletin 1995/38

(21)	Application number: 95301621.9

(22)	Date of filing: 13.03.1995

(51)	International Patent Classification (IPC)⁶: G09G 3/36, G09G 3/20, G09G 1/16

(84)	Designated Contracting States:
	DE ES FR GB IT NL SE

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Priority:

11.03.1994 AU PM4401/94
11.03.1994 AU PM4405/94
11.03.1994 AU PM4406/94
11.03.1994 AU PM4410/94
11.03.1994 AU PM4411/94
11.03.1994 AU PM4414/94
11.03.1994 AU PM4415/94
11.03.1994 AU PM4402/94
11.03.1994 AU PM4413/94
11.03.1994 AU PM4409/94
11.03.1994 AU PM4408/94
11.03.1994 AU PM4404/94

(71)	Applicant: CANON INFORMATION SYSTEMS RESEARCH AUSTRALIA PTY LTD.
	North Ryde, NSW 2113 (AU)

(72)	Inventor:
	Silverbrook, Kia New South Wales 2040 (AU)

(74)	Representative: Beresford, Keith Denis Lewis et al
	BERESFORD & Co. 2-5 Warwick Court High Holborn London WC1R 5DJ London WC1R 5DJ (GB)

(56)

References cited: :

(54)	Controller for a display with multiple common lines for each pixel

(57) There is disclosed a system (45, 55) for controlling a high resolution colour discrete level display device, wherein the display device can have multiple common lines (80, 81, 82) for each line of pixels. A frame buffer controller system (45) is disclosed which is adapted to utilise the multiple common lines in a number of different modes, producing a number of different output speeds for the display. Means (126, 127) are also disclosed for dithering the pixel data in accordance with the output modes. Further, the system is capable of displaying images, such as fonts or the like, at an increased resolution than that which would otherwise be possible.

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