(57) In a BiMOS semiconductor device, a bipolar transistor (36) has emitter and base electrodes
(88,43), formed by polycrystalline Si, isolated from each other by way of a sidewall
(56) and an insulator layer (54). As this insulator layer (54) acts as an offset during
the formation of the sidewall (56), its layer thickness can be made larger. Further,
as this insulator layer (54) is not provided in a MOS region of the device, its step
shape can be made smaller. Consequently, parasitic capacitance can be reduced while
the insulator layer can be made thicker. Thus, there can be achieved both fast operation
and high reliability of the bipolar transistor and, moreover, reduction in the reliability
of a MOS transistor can also be prevented.
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