Display apparatus with data communication channel

Abstract

 Display apparatus (130) for connection to a computer system (5) has a display screen (210) and a drive circuit (200) for generating an image on the display screen (210) in response to at least one video signal (R,G,B) from the computer system. A processor (270) controls the drive circuit as a function of control data from the computer system. The processor has interrupt servicing means (300') for detecting an interrupt signal. A communication channel (C) permits communication of control data between the processor and the computer system. An interrupt signal may be issued to the processor by input means (260). Switch means (310) selectively couples the interrupt servicing means of the processor to one of the input means and the communication channel.

Description

[0001] The present invention relates to display apparatus in which control data is communicated via a communication channel between a computer system and a display device.

[0002] The control data includes parameters for specifying the geometry and colour point of an image presented on the display device. In a display apparatus comprising a raster scanned display device such as for example a cathode ray tube (CRT) display device, the geometry parameters are determined by the rates and durations of horizontal or line and vertical or frame scan signals generated for producing the raster scan by electrical circuits in the display device. To generate the image, the scan signals are synchronised to video signals from a video adaptor in the computer system by synchronisation (sync) signals also generated by the video adaptor.

[0003] Some display devices can only operate in a single display mode characterised by a single set of parameters. Other display devices can be configured to operate in any one of a number of different display modes each characterised by a different set of parameters. The latter will hereinafter be referred to as multiple mode display devices.

[0004] Recent display devices include display processor logic in the form of a microprocessor configured by computer program microcode to control the operation of the drive circuitry according to input line and frame sync pulses from the host computer system and to image parameter settings manually input via a user control panel. The display processor typically comprises a serial data input. Image parameter data corresponding to various different display modes is pre-loaded into the display processor via the serial data input during initial set up and testing of the display device.

[0005] The display processor logic may be implemented at least partially by a custom-built microprocessor or by one of a large variety of different types of general-use microprocessors now available off the shelf from companies such as Motorola for use as 'building blocks' in the design of more complex microprocessor based systems. In both cases, the cost and physical size of microprocessors increases with an increase in the number of pins and it is thus usually desirable to keep the required number of pins to a minimum. Both off-the-shelf and custom built microprocessors commonly include keypad interrupts for receiving interrupt requests generated on actuation of the keys of an attached keypad or keyboard. Examples of off-the-shelf processors which provide this facility are the Motorola 68HC05G9 and 68HC05G10 Microcontroller Units.

[0006] European Patent Application No. 0 456 923 describes display apparatus comprising a display device for generating a visual output in response to input data signals defining data to be displayed. A computer generates the display data signals in a form specified by control data identifying the display device. An output port transmits the data signals from the computer to the display device and receives the control data from the display device at the computer. A memory is located in the display device for storing the control data in the form of a plurality of control codes. Communication logic communicates control codes between the memory and the output port in response to a command signal from the computer.

[0007] The display apparatus described in EP-A-0 456 923 increases the number of different display devices which can be identified and controlled by the computer system through the introduction of a control data communication channel between a memory in the display device and the video adaptor of the host computer system.

[0008] In accordance with the present invention, there is now provided display apparatus for connection to a computer system, the display apparatus including: a display screen; a drive circuit for generating an image on the display screen in response to at least one video signal from the computer system; a processor for controlling the drive circuit as a function of control data from the computer system, the processor having interrupt servicing means for detecting an interrupt signal; a communication channel for communicating control data between the processor and the computer system; and input means for issuing an interrupt signal to the processor; characterised in that the apparatus includes switch means for selectively coupling the interrupt servicing means of the processor to one of the input means and the communication channel.

[0009] By linking the communication channel to the display processor via the interrupt servicing means, the computer system to which display apparatus of the present invention is connected can provide the inputs normally provided by the operator through the operator means remotely. Display parameters such as brightness, contrast, image width, and image height which are normally adjusted user operator input means in the form of a key panel on the front of the display can now, in accordance with the present invention, be controlled remotely by software running on the computer system to which the display is attached. The present invention permits interrupts from the operator input means to be emulated by the computer system via the communication channel. In addition to receiving data from the computer system, the display processor can, in accordance with the present invention, transmit data to the computer system via the interrupt servicing means.

[0010] Preferably, buffer means is connected to the switch means and the communication channel for passing data between the processor and the communication channel.

[0011] The interrupt servicing means of the processor preferably includes an input port and an output port and the switch means is connected to the input port and the output port.

[0012] In a preferred embodiment of the present invention, the buffer means includes a first buffer connectable to the input port via the switch means and a second buffer connectable to the output port via the switch means.

[0013] The switch means may include a multiplexer for connecting the output port to one of the operator input means and second buffer and a demultiplexer for connecting one of the first buffer and the input means to the input port. Alternatively, the switch means may include a first cross-point switch matrix for connecting the output port to one of the input means and the second buffer and a second cross-point switch matrix for connecting one of the first buffer and the input means to the input port.

[0014] The communication channel preferably includes a serial data communication link. The serial data communication link may include, for convenience, a signal line of an interface cable (135) for supplying input video signals from the computer system.

[0015] The input means preferably includes a key-pad having a plurality of function keys.

[0016] It will be appreciated that the present invention extends to a data processing system including a computer system and display apparatus as described above.

[0017] A preferred embodiment of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Figure 1 is a block diagram of a computer system;

Figure 2 is a block diagram of a display device of the computer system;

Figure 3 is a block diagram of a communication interface circuit of the display device; and

Figure 4 is a block diagram of a display processor;

   Referring first to Figure 1, a computer system comprises a system unit 5 including a random access memory (RAM) 10, a read only store (ROS) 20, a central processing unit (CPU) 30, a communication adaptor 40, a display adaptor 70, a pointing device adaptor 80, a keyboard adaptor 90, and a mass storage device 100 as a hard disk drive or tape streamer for example, all interconnected by a bus architecture 60. System unit 5 is connected via adaptor 90 to a keyboard 110. A pointing device 120 such as a touch screen, a tablet, or a mouse is connected to system unit 5 via adaptor 80. System unit 5 is also connected via adaptor 70 and an interface cable 135 to a display 130 such as a cathode ray tube (CRT) display or a liquid crystal display for example. A network 50 of other system units is connected to system unit 5 via communication adaptor 40.

[0018] In operation, CPU 30 processes data stored in a combination of RAM 10 and mass storage device 100 under the control of computer program code stored in a combination of ROS 20, RAM 10, and mass storage device 100. Communication adaptor 40 controls transfer of data and computer program code between system unit 5 and other system units in network 50 through communication adaptor 40. Keyboard and mouse adaptors 90 and 80 permit data and instructions to be manually entered into system unit 5 from keyboard 110 and pointing device 120 respectively. Display adaptor 70 translates output data from system unit 5 into video signals, R, G and B, and horizontal and vertical picture synchronisation (sync) signals, H and V, for configuring display 130 to generate a visual data output. The R, G, B, H and V signals are communicated from display adaptor 70 to display device 135 via interface cable 135. Display adaptor 70 also communicates control data between system unit 5 and display device 130 along a serial data channel C in interface cable 135. Bus architecture 60 coordinates data transfer between RAM 10, ROS 20, CPU 30, storage device 100, and adaptors 40, 90, 80 and 70.

[0019] Referring now to Figure 2, display 130 comprises a display screen 210 in the form of a colour cathode ray display tube (CRT) connected to display drive circuitry 200. Display drive circuitry 200 comprises an Extra High Tension (EHT) generator 230 and a video amplifier 250 connected to display screen 210. Line and frame deflection coils 290 and 280 are disposed around the neck of the CRT. Deflection coils 290 and 280 are connected to line and frame scan circuits 220 and 240 respectively. Line scan circuit 220 and EHT generator 230 may each be in the form of a flyback circuit, the operation of which is well known by those skilled in the art. Furthermore, as is also well-known in the art, EHT generator 230 and line scan circuit 220 may be integrated in a single flyback circuit. A power supply (not shown) is connected via power supply rails (not shown) to EHT generator 230, video amplifier 250, and line and frame scan circuits 220 and 240. In use, the power supply provides electrical power on the supply rails from Line and Neutral connections (not shown) to the domestic electricity mains supply. The power supply may be in the form of a switch mode power supply, the operation of which is well-understood by those skilled in the art.

[0020] EHT generator 230, video amplifier 250, and line and frame scan circuits 220 and 240 are each connected to a display processor 270. Display processor 270 includes a microprocessor. A user control panel 260 is provided on the front of display device 130. Control panel 260 includes a plurality of manually operable switches. In accordance with the present invention, user control panel is connectable to key-pad interrupt lines of processor 270 via a communication interface circuit 310. Communication interface circuit 310 is connected to serial communication channel C of interface cable 135.

[0021] In operation, EHT generator 230 generates an electric field within CRT 210 for accelerating electrons in beams corresponding to the primary colours of red, green and blue towards the screen of CRT. Line and frame scan circuits 220 and 240 generate line and frame scan currents in deflection coils 290 and 280. The line and frame scan currents are in the form of ramp signals to produce time-varying magnetic fields that scan the electron beams across the screen of CRT 210 in a raster pattern. The line and frame scan signals are synchronised by line and frame scan circuits to input line and frame synchronisation (sync) signals H and V generated by video adaptor 70. Video amplifier 250 modulates the red, green and blue electron beams to produce an output display on CRT 210 as a function of corresponding red, green and blue input video signals R, G and B also generated by adaptor 70. Line and frame sync signals H and V and video signals R, G and B are supplied to display 130 from adaptor 70 along corresponding signal lines in interface cable 135. The signal lines of interface cable 135 terminate at the end remote from display device 130 in a connector (not shown) for detachably connecting the signal lines to adaptor 70. For compatibility, the connector is preferably a 15 pin D type connector although other connectors may be used.

[0022] Display processor 270 is configured to control the outputs of EHT generator 230, video amplifier 250, and line and frame scan circuits 220 and 240 via control links 275 as functions of preprogrammed display mode data and inputs from user control 260. The display mode data includes sets of preset image parameter values each corresponding to a different popular display mode such as, for example, 1024 X 768 pixels, 640 X 480 pixels, or 1280 X 1024 pixels. Each set of image display parameter values includes height and centring values for setting the output of frame scan circuit 240; and width and centring values for controlling line scan circuit 220. In addition, the display mode data includes common preset image parameter values for controlling the gain and cut-off of each of the red, green and blue channels of video amplifier 250; and preset control values for controlling the outputs of EHT generator 240. The image parameter values are selected by display processor 270 in response to mode information from adaptor 70. The mode information is delivered from adaptor 70 to display processor 270 via serial communication channel C. Display processor 270 processes the selected image parameter values to generate analog control levels on the control links. Adaptor 70 can send and receive control data to display device 130 via serial communication channel C. Initially, system unit 5 sends, via adaptor 70 and communication channel C, an interrogation code C to display device 130 . The interrogation code instructs display processor 270 to output on communication channel C identification data to adaptor 70. The identification data identifies display device 130 to system unit 5. In particular, the identification data specifies to system unit 5 the operating parameters of display device 130. The operating parameters tell system unit 5 how to drive display device 130. For example, the operating parameters include maximum and minimum sync frequencies acceptable to display device 130. Furthermore, interrogation codes may be sent to display device 130 from system unit 5 via communication channel when display device 130 is in use to monitor, for example, voltage levels in drive circuitry 200.

[0023] A user may also manually adjust the control levels controlling red green and blue video gains and cutoffs at video amplifier 250; and image width, height, and centring at line and frame scan circuits 220 and 240 via the user control panel 260. User control panel 260 includes a set of up/down control keys for each of image height, centring, width, brightness and contrast. It will be appreciated that similar control keys may also be provided for other functions such as East-West Pincushion distortion correction, trapezoidal distortion correction, and degaussing, for example.

[0024] The control keys are preferably in the form of push-buttons connected to key-pad interrupt inputs 320 to display processor 270. When, for example, the width up key is depressed, user control panel 260 issues a corresponding interrupt to display processor 270. The source of the interrupt is determined by display processor 270 via an interrupt polling routine. In response to the interrupt from the width key, display processor 270 progressively increases the corresponding analog control level sent to line scan circuit 220. The width of the image progressively increases. When the desired width is reached, the user releases the key. The removal of the interrupt is detected by display processor 270, and the digital value setting the width control level is retained. The height, centring, brightness and contrast setting can be adjusted by the user in similar fashion. User control panel 260 preferably further includes a store key. When the user depresses the store key, an interrupt is produced to which display processor 270 responds by storing in memory parameter values corresponding the current settings of the digital outputs to D to A convertor as a preferred display format. The user can thus programme into display 130 specific display image parameters according to personal preference. In addition, system unit 5 can send to display device 130 instruction codes via adaptor 70 and communication channel C. The instruction codes cause display processor 270 to perform the same functions as those provided by user control panel 260. This enables the output of display device 130 to be adjusted remotely under the control of computer software running in system unit 5.

[0025] Referring now to Figure 3, communication interface circuit 310 includes a multiplexer 500 having twelve input lines divided into two groups of six lines, six output lines, and a control line 550 for selecting one of the two groups of input lines for connection to corresponding ones of the output lines. Communication interface circuit 310 also includes another multiplexer 540 having eight output lines divided into two groups of four lines, four input lines, and a control input 560 for selecting one of the two groups of output lines for connection to corresponding ones of the four input lines. One group of output lines from multiplexer 540 is connected to corresponding parallel inputs of a four bit buffer 530. Buffer 530 has a serial output 580 to control logic 510. One group of input lines to multiplexers 500 is connected to corresponding parallel outputs of a six bit buffer 520. Buffer 520 has a serial input 570 connected to control logic 510. Control logic has control outputs connected to buffers 520 and 530 and to control inputs 550 and 560 of multiplexers 500 and 540 respectively. Communication channel C links control logic 510 to display adaptor 70 in system unit 5 via interface cable 135.

[0026] User control 260 includes a six by four matrix of keys. In accordance with the present invention, the keys are connectable via six input lines 310-315 and multiplexer 500 to one of buffer 520 and six processor pins (IP0 to IP5) of processor 270. The keys are also connectable via four output lines 301-304 and multiplexer 540 to one of buffer 530 and four processor output pins (OP0 to OP3) of processor 270. The operation of the keypad will now be described in the case where multiplexers 500 and 540 are switched to connect input lines 310-315 to processor pins IP0-IP5 and to connect output pins 301-304 to OP0-OP3. As will be described hereinafter, depression of one of the keys causes an interrupt signal on one of the six input lines which results in the issuing of a keypad interrupt request signal to the Central Processing Unit (CPU) of processor 270.

[0027] Figure 4 shows the major functional elements of processor 270. At the heart of processor 270 is the CPU 440 which includes an ALU, a program counter, a stack pointer and various internal registers. The CPU operates under the control of program(s) stored in ROM 490. Internal processor memory is provided in the form of RAM 480 and EEPROM 490. Oscillator and core timer unit 450 generates control and timing signals for routing to appropriate components of the processor 270 in order to control operation of the processor 270. Processor 270 also includes an interrupt servicing subsystem.

[0028] What follows is a brief description of the interrupt servicing subsystem of processor 270. Respectively connected to input pins IP0..5 and output pins OP0..3 are input port logic 400, including keypad interrupt hardware, and output port logic 410. Associated with the input and output ports are Input and Output Registers, 430 and 420. The Input Registers 430 include Keypad Status Register (KSR) which, when set, identifies the input line over which an interrupt signal was received. CPU 420 has access to the I/O Registers and in particular to the Keypad Status Register. Processor 270 is also designed to handle sources of interrupts other than those received via the processor input pins. These further interrupt sources are indicated generally at 460.

[0029] Returning to Figure 3, at each crossing point of input and output lines of user control 260 is a key. Depression of a key causes contact to be made between input and output lines at the crossing point. For example, depression of key 52 connects input line 314 with output line 301. Provided on each input line is a ten Kohm resistor connected to a 5 Volt supply which when the keypad is in quiescent state causes all input lines to be pulled high.

[0030] When the user control keypad circuitry is in quiescent state, all input lines are held high by the pull-up resistors. In addition, all output lines are held low by output port 410. When a key is depressed, the relevant input line undergoes a transition from high to low. The input line to stay low until the key is released.

[0031] A transition from high to low on one of the input lines, caused by actuation of a key, is sensed by the keypad interrupt logic in input hardware 270. The keypad status flag in Keypad Status Register is set for the activated input line and a keypad interrupt request is issued by the interrupt logic to the CPU. In response to the Keypad Interrupt Request, hardware in the CPU causes a jump to a preset memory location which specifies the interrupt service software routine.

[0032] In accordance with the present invention, communication interface circuit 310 enables data to transferred between communication channel C and processor 270 via keypad interrupt inputs IP0-IP5 and keypad interrupt outputs OP0-OP3.

[0033] To input data to processor 270 from communication channel C, control logic 510 sets control input 550 to configure multiplexer 500 to connect the six outputs of buffer 520 to inputs IP0-IP5. Control logic reads data from system unit 5 serially from communication channel C and loads it in successive six bit strings into buffer 520 via input 570. Upon loading each six bit string in to buffer 520, control logic 510 enables the outputs of buffer 520 thereby presenting the six bit string via multiplexer 550 to inputs IP0-IP5 of processor 270. Control logic 270 then reads the next six bit string of data from communication channel C into buffer 520 and the above sequence is repeated until all the data is transferred. It will be appreciated that buffer 520 may include a shift register for facilitating serial loading and parallel reading of data.

[0034] To output data from processor 270 to communication channel C, control logic 510 sets control input 560 to configure multiplexer 540 to connect the four parallel inputs of buffer 530 to outputs OP0-OP5. Control logic 510 loads 4 bit data words from processor 270 into buffer 530 in parallel. Control logic 510 then shifts each four bit data word, out of buffer 530 onto communication channel C via serial output 580. The four bit data is serially read from communication channel C by system unit 5 via adaptor 70. Control logic 510 then loads the next four bit data in parallel into buffer 530 and the above sequence is repeated until all data is transferred. It will be appreciated that buffer 540 may include a shift register for facilitating serial loading and parallel reading of data.

[0035] By linking communication channel C to processor 270 via the interrupt servicing subsystem of processor 270, system unit 5 can remotely provide the inputs normally provided by manually by the operator through user control 260. Display parameters such as brightness, contrast, image width, and image height which are normally adjusted by the user via user control 260 can thus, in accordance with the present invention, be controlled remotely by software running on system unit 5. The present invention permits interrupts from user control 260 to be emulated by system unit 5 via communication channel C. In addition to receiving data from system unit 5, processor 270 can, in accordance with the present invention, transmit data to system unit 5 via its interrupt servicing subsystem.

[0036] It will be appreciated that control logic 510 may be implemented by hard-wired logic; by a microprocessor device configured by computer program code; or by a combination of both hard-wired logic and a microprocessor configured by computer program code.

[0037] In the preferred embodiment of the present invention hereinbefore described data was routed between the interrupt inputs and outputs of processor 270 and communication channel C via multiplexers 500 and 560. However, it will be appreciated that, in other embodiments of the present invention, such routing may be provided by different data switching devices such as, for example, cross-point switching devices or cross-bar switching devices.

[0038] A preferred embodiment of the present invention has been hereinbefore described with reference to a cathode ray tube display device. It will, however, be appreciated that the present invention is equally applicable to other forms of display device such as, for example, liquid crystal display devices.

[0039] To summarise what has been described in detail above, in a preferred embodiment of the present invention, there is provided display apparatus (130) for connection to a computer system (5), including a display screen (210) and a drive circuit (200) for generating an image on the display screen (210) in response to at least one video signal (R,G,B) from the computer system. A processor (270) controls the drive circuit as a function of control data from the computer system. The processor has interrupt servicing means (300') for detecting an interrupt signal. A communication channel (C) permits communication of control data between the processor and the computer system. An interrupt signal may be issued to the processor by input means (260). Switch means (310) selectively couples the interrupt servicing means of the processor to one of the input means and the communication channel.

Claims

1. Display apparatus (130) for connection to a computer system (5), the display apparatus including: a display screen (210); a drive circuit (200) for generating an image on the display screen (210) in response to at least one video signal (R,G,B) from the computer system; a processor (270) for controlling the drive circuit as a function of control data from the computer system, the processor having interrupt servicing means (300') for detecting an interrupt signal; a communication channel (C) for communicating control data between the processor and the computer system; and input means (260) for issuing an interrupt signal to the processor; characterised in that the apparatus includes switch means (310) for selectively coupling the interrupt servicing means of the processor to one of the input means and the communication channel.

2. Apparatus as claimed in claim 1, including buffer means (520,530) connected to the switch means and the communication channel for passing data between the processor and the communication channel.

3. Apparatus as claimed in claim 2, wherein the interrupt servicing means of the processor includes an input port (400) and an output port (410) and the switch means is connected to the input port and the output port.

4. Apparatus as claimed in claim 3, wherein the buffer means includes a first buffer (520) connectable to the input port via the switch means and a second buffer (530) connectable to the output port via the switch means.

5. Apparatus as claimed in claim 4, wherein the switch means includes a multiplexer (540) for connecting the output port to one of the operator input means and second buffer and a demultiplexer (500) for connecting one of the first buffer and the input means to the input port.

6. Apparatus as claimed in claim 4, wherein the switch means includes a first cross-point switch for connecting the output port to one of the input means and the second buffer and a second cross-point switch for connecting one of the first buffer and the input means to the input port.

7. Apparatus a claimed in any preceding claim, wherein the communication channel (C) includes a serial data communication link.

8. Apparatus as claimed in claim 7, wherein the serial data communication link includes a signal line of an interface cable (135) for supplying input video signals from the computer system.

9. Apparatus as claimed in any preceding claim, wherein the input means includes a key-pad having a plurality of function keys.

10. A data processing system including a computer system (5) and display apparatus (130) as claimed in any preceding claim connected to the computer system.

Drawing