LOGICAL THREE-DIMENSIONAL INTERCONNECTIONS BETWEEN INTEGRATED CIRCUIT CHIPS USING A TWO-DIMENSIONAL MULTI-CHIP MODULE PACKAGE - Patent 0698294

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EP 0 698 294 A1

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(43)	Date of publication:
	28.02.1996 Bulletin 1996/09

(21)	Application number: 95908601.0

(22)	Date of filing: 20.01.1995

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International Patent Classification (IPC):

H01L 23/ 538^{( . )}
H03K 19/ 177^{( . )}

H01L 25/ 065^{( . )}

(86)	International application number:
	PCT/US1995/000796

(87)	International publication number:
	WO 1995/025348 (21.09.1995 Gazette 1995/40)

(84)	Designated Contracting States:
	DE FR GB

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Priority:

15.03.1994 US 19940213146

(71)	Applicant: NATIONAL SEMICONDUCTOR CORPORATION
	Sunnyvale, CA 95086-3737 (US)

(72)	Inventors:
	SUTHERLAND, James Santa Clara, CA 94087 (US) GARVERICK, Timothy, L. Cupertino, CA 95014 (US) TAKIAR, Hem, P. Fremont, CA 94539 (US) REYLING, George, F., Jr. Saratoga, CA 95070 (US)

(74)	Representative: Bowles, Sharon Margaret, et al
	BOWLES HORTON Felden House Dower Mews High Street Berkhamsted Hertfordshire HP4 2BL Berkhamsted Hertfordshire HP4 2BL (GB)

(54)	LOGICAL THREE-DIMENSIONAL INTERCONNECTIONS BETWEEN INTEGRATED CIRCUIT CHIPS USING A TWO-DIMENSIONAL MULTI-CHIP MODULE PACKAGE