ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE - Patent 0705485

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EP 0 705 485 A1

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(43)	Date of publication:
	10.04.1996 Bulletin 1996/15

(21)	Application number: 94920207.0

(22)	Date of filing: 13.06.1994

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International Patent Classification (IPC):

H01L 23/ 12^{( . )}
H01L 23/ 16^{( . )}
H01L 23/ 433^{( . )}
H01L 23/ 50^{( . )}

H01L 23/ 057^{( . )}
H01L 23/ 36^{( . )}
H01L 23/ 495^{( . )}

(86)	International application number:
	PCT/US1994/006739

(87)	International publication number:
	WO 1995/000973 (05.01.1995 Gazette 1995/02)

(84)	Designated Contracting States:
	DE FR GB NL

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Priority:

23.06.1993 US 19930082122
17.12.1993 US 19930169617

(71)	Applicant: VLSI TECHNOLOGY, INC.
	San Jose California 95131 (US)

(72)	Inventors:
	GROOVER, Richard Santa Clara, CA 95054 (US) SHU, William Sunnyvale, CA 94086 (US) LEE, Sang, S. Sunnyvale, CA 94087 (US) FUJIMOTO, George Santa Clara, CA 95051 (US)

(74)	Representative: Kahler, Kurt, Dipl.-Ing.
	Patentanwälte Kahler, Käck, Fiener & Sturm P.O. Box 12 49 D-87712 Mindelheim D-87712 Mindelheim (DE)

(54)	ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE