LOW POWER, HIGH PERFORMANCE, ON-CHIP CACHE WITH NO STALL AFTER A WRITE HIT - Patent 0711437

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EP 0 711 437 A1

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(43)	Date of publication:
	15.05.1996 Bulletin 1996/20

(21)	Application number: 95916415.0

(22)	Date of filing: 14.04.1995

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International Patent Classification (IPC):

G06F 12/ 08^{( . )}

(86)	International application number:
	PCT/US1995/004669

(87)	International publication number:
	WO 1995/033238 (07.12.1995 Gazette 1995/52)

(84)	Designated Contracting States:
	DE FR GB

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Priority:

31.05.1994 US 19940251796

(71)	Applicant: NATIONAL SEMICONDUCTOR CORPORATION
	Sunnyvale, CA 95086-3737 (US)

(72)	Inventors:
	INTRATER, Gideon 52413 Ramat-Gan (IL) AZMANOV, Ziv Cupertino, CA 95014 (US)

(74)	Representative: Horton, Andrew Robert Grant, et al
	BOWLES HORTON Felden House Dower Mews High Street Berkhamsted Hertfordshire HP4 2BL Berkhamsted Hertfordshire HP4 2BL (GB)

(54)	LOW POWER, HIGH PERFORMANCE, ON-CHIP CACHE WITH NO STALL AFTER A WRITE HIT